Self-Aligned Spacer Contact

• US 20080272410A1
• Filed: 05/02/2007
• Published: 11/06/2008
• Est. Priority Date: 05/02/2007
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chung-Te
• Application Number:
  US11/743,519
• Publication Number:
  US 20080272410A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A metal-oxide-semiconductor field-effect transistor (MOSFET) having self-aligned spacer contacts is provided. In accordance with embodiments of the present invention, a transistor, having a gate electrode and source/drain regions formed on opposing sides of the gate electrode, is covered with a first dielectric layer. A first contact opening is formed in the first dielectric layer to expose at least a portion of one of the source/drain regions. A second dielectric layer is formed over the first dielectric layer. Thereafter, an inter-layer dielectric layer is formed over the second dielectric layer and a second contact opening is formed through the inter-layer dielectric layer. In an embodiment, an etch-back process may be performed on the second dielectric layer prior to forming the inter-layer dielectric layer.

Claims

1. A semiconductor device comprising:

a transistor on a substrate, the transistor comprising a gate electrode and source/drain regions on opposing sides of the gate electrode;

a first dielectric layer over the transistor;

a first contact opening in the first dielectric layer over at least a portion of one of the source/drain regions;

a second dielectric layer along sidewalls of the first contact opening;

an inter-layer dielectric (ILD) layer over the first dielectric layer; and

a second contact opening at least partially within the first contact opening.

2. The semiconductor device of claim 1, wherein the first dielectric layer comprises silicon nitride.

3. The semiconductor device of claim 1, wherein the second dielectric layer along sidewalls of the first contact opening extends over at least a portion of the gate electrode.

4. The semiconductor device of claim 1, wherein the second dielectric layer comprises silicon nitride.

5. The semiconductor device of claim 1, wherein the second dielectric layer comprises spacers alongside the first contact opening.

6. The semiconductor device of claim 1, wherein the first dielectric layer has a thickness from about 200 Å

to about 1000 Å

.

7. The semiconductor device of claim 1, wherein the second dielectric layer has a thickness from about 40 Å

to about 400 Å

.

8. The semiconductor device of claim 1, wherein the first dielectric layer comprises a high stress film.

9. A semiconductor device comprising:

a PMOS transistor on a substrate, the PMOS transistor comprising a first gate electrode and first source/drain regions on opposing sides of the first gate electrode;

an NMOS transistor on the substrate, the NMOS transistor comprising a second gate electrode and second source/drain regions on opposing sides of the second gate electrode;

a first stress layer over the PMOS transistor, the first stress layer being a compressive stress film;

a first contact opening in the first stress layer over at least a portion of one of the first source/drain regions;

a second stress layer over the NMOS transistor, the second stress layer being a tensile stress film;

a second contact opening in the second stress layer over at least a portion of one of the second source/drain regions;

a first dielectric layer over the first stress layer and the second stress layer;

an inter-layer dielectric (ILD) layer over the first dielectric layer;

a third contact opening through the ILD layer at least partially within the first contact opening; and

a fourth contact opening through the ILD layer at least partially within the second contact opening.

10. The semiconductor device of claim 9, wherein the first dielectric layer comprises silicon nitride.

11. The semiconductor device of claim 9, wherein the first dielectric layer comprises spacers alongside the first contact opening and the second contact opening, the first dielectric layer not extending over a bottom surface of the first contact opening and a bottom surface of the second contact opening.

12. The semiconductor device of claim 9, wherein the first stress layer and the second stress layer have a thickness from about 200 Å

to about 1000 Å

.

13. The semiconductor device of claim 9, wherein the first dielectric layer has a thickness from about 40 Å

to about 400 Å

.

14. A semiconductor device comprising:

a transistor on a substrate, the transistor comprising a gate electrode and source/drain regions on opposing sides of the gate electrode;

a first dielectric layer over the transistor;

a first contact opening in the first dielectric layer over at least a portion of one of the source/drain regions;

spacers along sidewalls of the first contact opening;

an inter-layer dielectric (ILD) layer over the first dielectric layer; and

a second contact opening at least partially within the first contact opening.

15. The semiconductor device of claim 14, wherein the first dielectric layer comprises silicon nitride.

16. The semiconductor device of claim 14, wherein the spacers comprise silicon nitride.

17. The semiconductor device of claim 14, wherein the first dielectric layer has a thickness from about 200 Å

to about 1000 Å

.

18. The semiconductor device of claim 14, wherein the spacers have a thickness from about 40 Å

to about 400 Å

.

19. The semiconductor device of claim 14, wherein the first dielectric layer comprises a high stress film.

20. The semiconductor device of claim 14, wherein the first dielectric layer comprises a compressive stress film.