Nonvolatile Memory Device Having Fast Erase Speed And Improved Retention Characteristics And Method For Fabricating The Same

• US 20080272424A1
• Filed: 11/15/2007
• Published: 11/06/2008
• Est. Priority Date: 05/03/2007
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Tae Yoon, Kim, Yong Top, Lee, Seung Ryong, Yang, Hong Seon, Kim, Yong Soo, Joo, Moon Sig
• Application Number:
  US11/940,647
• Publication Number:
  US 20080272424A1
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/3145 formed by deposition from a gas or vapour
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator

Abstract

Disclosed herein is a nonvolatile memory device that includes a substrate, a tunneling layer over the substrate, a charge trapping layer over the tunneling layer, an insulating layer for improving retention characteristics over the charge trapping layer, a blocking layer over the insulating layer, and a control gate electrode over the blocking layer. Also disclosed herein is a method of making the device.

Claims

1. A nonvolatile memory device comprising:

a substrate;

a tunneling layer formed over the substrate;

a charge trapping layer formed over the tunneling layer;

an insulating layer formed over the charge trapping layer for improving retention characteristics of the charge trapping layer;

a blocking layer formed over the insulating layer; and

a control gate electrode formed over the blocking layer.

2. The nonvolatile memory device according to claim 1, wherein the insulating layer comprises an oxide layer or a nitride layer.

3. The nonvolatile memory device according to claim 1, wherein the charge trapping layer has a stacked structure comprising a stoichiometric silicon nitride layer and a silicon-rich silicon nitride layer stacked over the stoichiometric silicon nitride layer.

4. The nonvolatile memory device according to claim 1, wherein the insulating layer comprises an oxide layer, and the charge trapping layer has a stacked structure comprising a stoichiometric silicon nitride layer and a silicon-rich silicon nitride layer stacked over the stoichiometric silicon nitride layer, wherein the charge trapping layer has a ratio of silicon to nitride of 3:

4 to 1;

1.

5. The nonvolatile memory device according to claim 1, wherein the insulating layer comprises an oxide layer, the oxide layer comprising a silicon oxynitride layer.

6. The nonvolatile memory device according to claim 5, wherein the silicon oxynitride layer has a thickness of 1 Å

to 10 Å

.

7. The nonvolatile memory device according to claim 5, further comprising a second silicon oxynitride layer disposed between the tunneling layer and charge trapping layer.

8. The nonvolatile memory device according to claim 1, wherein the blocking layer comprises an aluminum oxide layer, and the control gate electrode comprises a metal layer.

9. The nonvolatile memory device according to claim 1, wherein the insulating layer comprises a nitride layer, and the charge trapping layer has a stacked structure comprising a stoichiometric silicon nitride layer and a silicon-rich silicon nitride layer stacked over the stoichiometric silicon nitride layer, wherein the charge trapping layer has a ratio of silicon to nitride of 0:

85;

1 to 2;

1.

10. The nonvolatile memory device according to claim 1, wherein the insulating layer comprises a nitride layer, the nitride layer comprising a stoichiometric silicon nitride layer.

11. The nonvolatile memory device according to claim 10, wherein the stoichiometric silicon nitride layer has a thickness of 1 Å

to 10 Å

.

12. A nonvolatile memory device comprising:

a substrate;

a tunneling layer formed over the substrate;

a charge trapping layer formed over the tunneling layer;

an oxide layer formed over the charge trapping layer for improving retention characteristics of the charge trapping layer;

a blocking layer formed over the insulating layer; and

a control gate electrode formed over the blocking layer.

13. A nonvolatile memory device comprising:

a substrate;

a tunneling layer formed over the substrate;

a charge trapping layer formed over the tunneling layer;

a nitride layer formed over the charge trapping layer for improving retention characteristics of the charge trapping layer;

a blocking layer formed over the insulating layer; and

a control gate electrode formed over the blocking layer.

14. A method for fabricating a nonvolatile memory device, comprising:

forming a tunneling layer over a substrate;

forming a charge trapping layer over the tunneling layer;

forming an insulating layer over the charge trapping layer for improving retention characteristics of the charge trapping layer;

forming a blocking layer over the insulating layer; and

forming a control gate electrode over the blocking layer.

15. The method according to claim 14, wherein the charge trapping layer has a stacked structure comprising a stoichiometric silicon nitride layer and a silicon-rich silicon nitride layer stacked over the stoichiometric silicon nitride layer.

16. The method according to claim 14, wherein the insulating layer has a thickness of 1 Å

to 10 Å

.

17. The method according to claim 14, wherein the step of forming the insulating layer comprises performing an oxidation process for an upper portion of the charge trapping layer to form an oxide layer.

18. The method according to claim 17, wherein the oxidation process comprises performing rapid thermal processing in an oxygen (O₂) atmosphere at a temperature of about 600°

C. to 950°

C. for about 10 seconds to 60 seconds.

19. The method according to claim 14, wherein the step of forming the insulating layer comprises performing a nitration process on an upper portion of the charge trapping layer to form a stoichiometric silicon layer.

20. The method according to claim 19, wherein the nitration process comprises:

performing rapid thermal processing in an ammonia (NH₃) atmosphere at a temperature of about 600°

C. to 950°

C. for about 10 seconds to 60 seconds; and

performing rapid thermal processing in a vacuum nitrogen (N₂) atmosphere at a temperature of about 600°

C. to 950°

C. for about 10 seconds to 60 seconds to achieve a surface stabilization.

21. The method according to claim 19, wherein the nitration process comprises performing a plasma nitration method.

22. The method according to claim 14, wherein the blocking layer comprises an aluminum oxide layer, and the control gate electrode comprises a metal layer.

23. The method of claim 14, further comprising:

forming a first silicon oxynitride layer over the tunneling layer and before the step of forming the charge trapping layer;

wherein;

the charge trapping layer comprises a silicon nitride layer; and

,

the insulating layer comprises a second silicon oxynitride layer.