Semiconductor device and method of fabricating the same
First Claim
1. A method of fabricating a semi conductor device, the method comprising:
- forming a first stress film covering a first gate electrode and first source/drain areas of a first transistor area of a semiconductor substrate and at least a portion of a third gate electrode of an interface area between the first transistor area and a second transistor area;
forming a second stress film covering a second gate electrode and second source/drain areas of the second transistor area of the semiconductor substrate and overlapping at least a portion of the first stress film on the third gate electrode of the interface area;
forming an interlayer insulating film on the semiconductor substrate;
patterning the interlayer insulating film to form a plurality of preliminary contact holes through which the first stress film on the first gate electrode and the first source/drain areas and the second stress film on the second and the third gate electrodes and the second source/drain areas are exposed;
filling the plurality of preliminary contact holes with a filling material;
removing the filling material to expose the second stress film in the interface area while the filling material remains in the preliminary contact holes of the first transistor area and the second transistor area;
removing the exposed second stress film of the interface area;
removing the remaining filling material to expose the first stress film of the first transistor area and the second stress film of the second transistor area; and
removing the exposed first stress film and second stress film to form a plurality of contact holes through which the first, the second, and the third gate electrodes, and the first and the second source/drain areas are exposed.
1 Assignment
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Accused Products
Abstract
A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed.
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Citations
21 Claims
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1. A method of fabricating a semi conductor device, the method comprising:
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forming a first stress film covering a first gate electrode and first source/drain areas of a first transistor area of a semiconductor substrate and at least a portion of a third gate electrode of an interface area between the first transistor area and a second transistor area; forming a second stress film covering a second gate electrode and second source/drain areas of the second transistor area of the semiconductor substrate and overlapping at least a portion of the first stress film on the third gate electrode of the interface area; forming an interlayer insulating film on the semiconductor substrate; patterning the interlayer insulating film to form a plurality of preliminary contact holes through which the first stress film on the first gate electrode and the first source/drain areas and the second stress film on the second and the third gate electrodes and the second source/drain areas are exposed; filling the plurality of preliminary contact holes with a filling material; removing the filling material to expose the second stress film in the interface area while the filling material remains in the preliminary contact holes of the first transistor area and the second transistor area; removing the exposed second stress film of the interface area; removing the remaining filling material to expose the first stress film of the first transistor area and the second stress film of the second transistor area; and removing the exposed first stress film and second stress film to form a plurality of contact holes through which the first, the second, and the third gate electrodes, and the first and the second source/drain areas are exposed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor device comprising:
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a semiconductor substrate including a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode; a first stress film covering the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area; a second stress film covering the second gate electrode and the second source/drain areas of the second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area; an interlayer insulating film formed on the first and the second stress film; a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas; a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas; and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. wherein a depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification