Method and circuit for down-converting a signal

• US 20080272441A1
• Filed: 01/09/2008
• Published: 11/06/2008
• Est. Priority Date: 10/21/1998
• Status: Active Grant

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Cook, Robert W., Rawlins, Gregory S., Bultman, Michael J., Sorrells, David F., Moses, Charley D., Looke, Richard C., Rawlins, Michael W.
• Granted Patent: US 7,936,022 B2
• Time in Patent Office: Days
• US Class Current: 257/387
• CPC Class Codes: H03C 1/62 Modulators in which amplitude of carrier component in output is dependent upon strength of modulating signal, e.g. no carrier output when no modulating signal is present H03C1/28 - H03C1/34, H03C1/46, H03C1/48 take precedence
• CPC Class Codes: H03D 7/00 Transference of modulation from one carrier to another, e.g. frequency-changing H03D9/00, H03D11/00 take precedence; dielectric amplifiers, magnetic amplifiers, parametric amplifiers used as a frequency-changers H03F
• CPC Class Codes: H03D 7/1441 using field-effect transistors H03D7/145 takes precedence
• CPC Class Codes: H03D 7/1475 Subharmonic mixer arrangements
• CPC Class Codes: H04B 1/0025 using a sampling rate lower than twice the highest frequency component of the sampled signal for demodulation of angle-modulated signals H03D3/006
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 7/12 Frequency diversity
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/00 Modulated-carrier systems
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/148 using filters, including PLL-type filters
• CPC Class Codes: H04L 27/156 with demodulation using temporal properties of the received signal, e.g. detecting pulse width
• CPC Class Codes: H04L 27/2672 Frequency domain
• CPC Class Codes: H04L 27/3881 using sampling and digital processing, not including digital systems which imitate heterodyne or homodyne demodulation

Abstract

Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal are described herein. Briefly stated, such methods, systems, and apparatuses operate by receiving an EM signal and an aliasing signal having an aliasing rate. The EM signal is aliased according to the aliasing signal to down-convert the EM signal. The term aliasing, as used herein, refers to both down-converting an EM signal by under-sampling the EM signal at an aliasing rate, and down-converting an EM signal by transferring energy from the EM signal at the aliasing rate. In an embodiment, the EM signal is down-converted to an intermediate frequency signal. In another embodiment, the EM signal is down-converted to a demodulated baseband information signal. In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated signal or an amplitude modulated signal.

Claims

1. A metal oxide semiconductor field effect transistor having a reduced gate extension and reduced gate pad extension, comprising:

a source region;

a drain region;

a channel region disposed between said source and drain regions;

an insulating layer disposed above said channel region;

a gate disposed above said insulating layer, said gate including a gate region disposed above said channel region and above a portion of said source and drain regions, said gate region including first and second ends disposed opposite one another, said gate including a gate pad extension coupled between said gate region first end and a gate pad, said gate pad extension and said gate pad extending over a first area adjacent to said channel region, said gate including a gate extension coupled to said gate region second end and extending over a second area adjacent to said channel region;

wherein said gate pad extension and/or said gate extension are minimized in length and/or area, thereby reducing parasitic capacitances.

3. The metal oxide semiconductor field effect transistor of claim 1, wherein the insulating layer comprises a metal-oxide insulator.

4. The metal oxide semiconductor field effect transistor of claim 1, wherein the gate pad extension is of non-zero length to separate the gate pad from the source region and the drain region.

5. The metal oxide semiconductor field effect transistor of claim 1, wherein an area of the gate pad depends upon parasitic capacitances existing in the metal oxide semiconductor field effect transistor.

6. The metal oxide semiconductor field effect transistor of claim 1, wherein the metal oxide semiconductor field effect transistor is at least one of an n-channel enhancement mode metal oxide semiconductor field effect transistor and a depletion mode metal oxide semiconductor field effect transistor.

7. The metal oxide semiconductor field effect transistor of claim 1, wherein the metal oxide semiconductor field effect transistor is a switch.

8. The metal oxide semiconductor field effect transistor of claim 1, wherein the source and the drain are interchangeable.

9. The metal oxide semiconductor field effect transistor of claim 1, wherein the gate region, the gate pad extension, and the gate pad are arranged in a configuration substantially similar to FIG. 128C.

2. A method of fabricating a metal oxide semiconductor field effect transistor having reduced gate extension and reduced gate pad extensions, comprising:

(1) fabricating a channel region between a source region and a drain region;

(2) fabricating an insulating layer above said channel region;

(3) fabricating a gate above said insulating layer, said gate including a gate region disposed above said channel region, said gate region including first and second ends disposed opposite one another, said gate including a gate pad extension coupled between said gate region first end and a gate pad, said gate pad extension and said gate pad extending over a first area adjacent to said channel region, said gate including a gate extension coupled to said gate region second end and extending over a second area adjacent to said channel region, said gate fabrication includes minimizing a length and/or width of said gate pad extension and/or said gate extension, thereby reducing parasitic capacitances.

10. The method of claim 2, comprising:

(3) controlling a current in the channel region by applying a voltage at the gate to result in a variation of an overall conductivity of the metal oxide semiconductor field effect transistor.

11. The method of claim 2, wherein steps (1)-(3) are performed using an ion implantation/diffusion process.

12. The method of claim 2, wherein step (3) comprises preventing the gate from shorting the channel region between the source region and the drain region thereby avoiding a damage to the metal oxide semiconductor field effect transistor.