SEMICONDUCTOR DIE PACKAGE AND INTEGRATED CIRCUIT PACKAGE AND FABRICATING METHOD THEREOF

• US 20080272469A1
• Filed: 04/08/2008
• Published: 11/06/2008
• Est. Priority Date: 05/02/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Kwak, Kyu-Sub, Lee, Jae-Hyuck
• Granted Patent: US 8,043,892 B2
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/19107 off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor die package includes a substrate, a semiconductor die mounted on the substrates a molding covering the semiconductor die and which is formed on the substrate and a conductive layer laminated on the molding.

Claims

1. A semiconductor die package comprising:

a substrate;

a semiconductor die mounted on the substrate;

a molding covering the semiconductor die and formed on the substrate; and

a conductive layer laminated on the molding, said molding and conductive layer being selectively etched around said die.

2. The semiconductor die package as claimed in claim 1, wherein the substrate comprises:

at least one electrical terminal electrically connected to the semiconductor die; and

at least one ground terminal for electrically grounding the conductive layer.

3. The semiconductor die package as claimed in claim 1, wherein the conductive layer is laminated on an outer surface of the molding.

4. The semiconductor die package as claimed in claim 2, further comprising:

at least one wiring for electrically connecting the conductive layer and the ground terminal.

5. The semiconductor die package as claimed in claim 2, wherein the ground terminal is electrically connected to the conductive layer.

6. An integrated circuit package comprising:

a printed circuit board provided with at least one ground terminal, at least one electrical terminal, and at least one electronic component electrically connected to the ground and the electrical terminal;

a semiconductor die package mounted on the printed circuit board;

a molding covering the semiconductor die package and the electronic component, said molding being formed on the printed circuit board; and

a conductive layer laminated onto the molding, said molding and conductive layer being selective etched.

7. The integrated circuit package as claimed in claim 6, further comprising:

at least one electrical wiring for electrically connecting the ground terminal and the conductive layer.

8. The integrated circuit package as claimed in claim 6, wherein the conductive layer is laminated onto an outer surface of the molding.

9. A method for fabricating a semiconductor die package, the method comprising:

forming circuit patterns including ground and electrical terminals on a substrate;

mounting multiple semiconductor dies on the substrate;

electrically connecting adjacent ground terminals by electrical wirings;

forming a molding covering the circuit patterns and the semiconductor dies on the substrate;

cutting the electrical wirings connecting adjacent ground terminals and the molding; and

laminating a conductive layer onto an outer surface of the molding.

10. The method as claimed in claim 9, wherein the molding is cut wherein the electrical wirings connected to adjacent ones of the ground terminals are exposed to side surfaces of the molding.

11. The method as claimed in claim 9, wherein the conductive layer is laminated wherein the conductive layer is electrically connected to the electrical wirings exposed to the outer surface of the molding.

12. A method for fabricating a semiconductor die package, the method comprising:

forming circuit patterns including ground and electrical terminals on a substrate;

mounting multiple semiconductor dies on the substrate;

forming a molding covering the circuit patterns and the semiconductor dies on the substrate;

cutting the ground terminals and the molding; and

laminating a conductive layer on an outer surface of the molding.

13. A method for fabricating an integrated circuit package, the method comprising:

forming circuit patterns including ground and electrical terminals on a printed circuit board;

mounting multiple semiconductor die packages on the printed circuit board;

electrically connecting adjacent ground terminals from the circuit patterns by electrical wirings;

forming a molding covering the circuit patterns and the semiconductor die packages on the printed circuit board;

etching the molding and selected electrical wirings between the ground terminals and the molding; and

laminating a conductive layer on an outer surface of the molding, said conductive layer in electrical contact with said exposed electrical wiring ends.

14. An EMI protected semiconductor die package comprising:

a substrate;

at least one semiconductor die mounted on the substrate;

at least one electrical terminal electrically connected to the semiconductor die;

a plurality of ground terminals, wherein adjacent ground terminals are electrically connected by electrical wiring,

a molding covering the semiconductor die and formed on the substrate;

a conductive layer laminated on the molding, said molding and conductive layer being selectively etched to expose wire ends of adjacent ground connections.

15. The semiconductor die package as claimed in claim 14, wherein the conductive layer is laminated on an outer surface of the molding.

16. The semiconductor die package as claimed in claim 15, wherein said exposed wire ends are in electrical contact with said conductive layer.