Package-on-Package Using Through-Hole Via Die on Saw Streets

• US 20080272477A1
• Filed: 06/26/2007
• Published: 11/06/2008
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: KUAN, Heap Hoe, DO, Byung Tai, CHOW, Seng Guan
• Granted Patent: US 7,723,159 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48472 : the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.

Claims

1. A semiconductor package-on-package (PoP) device, comprising:

a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die, the first die disposed over a substrate or leadframe structure;

a first semiconductor package electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure; and

an encapsulant formed over a portion of the first die and the first semiconductor package.

2. The semiconductor device of claim 1, further including a second die or a second semiconductor package electrically connected to the first die.

3. The semiconductor device of claim 2, wherein the second die includes a flip chip die, and the second semiconductor package further includes a quad flat nonlead package (QFN), a small outline nonlead package (SON), a quad flat package (QFP), a land grid array device (LGA), or a ball grid array device (BGA).

4. The semiconductor device of claim 1, wherein the first semiconductor package is an inverted package device.

5. The semiconductor device of claim 4, wherein the inverted package is disposed between the first die and the substrate or leadframe structure.

6. The semiconductor device of claim 1, further including a interposer structure formed over the first die to electrically connect the first semiconductor package to the first die.

7. The semiconductor device of claim 1, wherein the first semiconductor package includes a topside-up flip chip die structure.

8. The semiconductor device of claim 1, wherein the first semiconductor package includes a fan-in package-on-package device (Fi-PoP).

9. The semiconductor device of claim 8, further including a second die or a second semiconductor package electrically connected to the Fi-PoP device.

10. The semiconductor device of claim 9, wherein the second die includes a flip chip die, and the second semiconductor package further includes a quad flat nonlead package (QFN), a small outline nonlead package (SON), a quad flat package (QFP), a land grid array device (LGA), or a ball grid array device (BGA).

11. The semiconductor device of claim 3, wherein the second semiconductor package is electrically coupled to the first die using a bump partially exposed from the encapsulant.

12. The semiconductor device of claim 3, wherein a cavity is formed in a portion of the substrate or leadframe structure to receive the second die.

13. A method of forming a semiconductor device, comprising:

providing a second, bumped die which is disposed over a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die;

providing a bump disposed over the THV;

providing an encapsulation covering a top portion of the THV and the bumped die, while exposing a portion of the bump and a bottom portion of the first die to constitute a first package of a plurality of packages; and

stacking the first package and a second package of the plurality of packages by connecting the bump of the first package to the THV of the second package.

14. The method of claim 13, wherein the second, bumped die further includes a wire bond die.

15. The method of claim 14, wherein the second, bumped die is integrated into a quad flat nonlead package (QFN), a small outline nonlead package (SON), a quad flat package (QFP), a land grid array device (LGA), or a ball grid array device (BGA).

16. A method of forming a semiconductor device, comprising:

providing a first die incorporating a through-hole via (THV) disposed along a peripheral surface;

providing a bump disposed over a top surface of the first die, or disposed over the THV;

providing an encapsulation covering a portion of the first die and the bump;

exposing the bump by removing a portion of the encapsulation; and

stacking a second die or a first package onto the exposed bump.

17. The method of claim 16, wherein the second die further is a wire bond die.

18. The method of claim 16, wherein the first package further includes a quad flat nonlead package (QFN), a small outline nonlead package (SON), a quad flat package (QFP), a land grid array device (LGA), or a ball grid array device (BGA).

19. A method of forming a semiconductor device, comprising:

providing a first die incorporating a through-hole via (THV) disposed along a peripheral surface, the THV connected by a metal trace to a bond pad;

disposing an interconnect pad over a top surface of the first die;

providing an encapsulation covering a portion of the THV, metal trace, and bond pad, while exposing a portion of the interconnect pad and a bottom surface of the first die; and

stacking a second die or a first package onto the interconnect pad.

20. The method of claim 19, further including providing a bump disposed over a top surface of the first die, or disposed over the THV.

21. The method of claim 19, wherein the second die further is a wire bond die.

22. The method of claim 19, wherein the first package further includes a quad flat nonlead package (QFN), a small outline nonlead package (SON), a quad flat package (QFP), a land grid array device (LGA), or a ball grid array device (BGA).

23. The method of claim 19, wherein stacking the second die or the first package onto the interconnect pad renders a first package of a plurality of packages.

24. The method of claim 23, further including stacking a second package of the plurality of packages above the first package.

25. The method of claim 24, wherein the bump electrically connects a top surface of the THV of the first package to a bottom surface of the THV of the second package.