Through-wafer vias

• US 20080272499A1
• Filed: 05/03/2007
• Published: 11/06/2008
• Est. Priority Date: 05/03/2007
• Status: Active Grant

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Teledyne Licensing, LLC
• Inventors: DeNatale, Jeffrey F., Lauxtermann, Stefan C.
• Granted Patent: US 7,829,462 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A through-wafer via interconnect region is in a circuit portion of a wafer, the circuit portion including at least one electrically conducting metal layer and configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit. Within the metal layer in the circuit portion, the metal is removably distributed such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.

Claims

1. A through-wafer via interconnect region, the via region being located within a circuit portion of a wafer, the circuit portion including at least one electrically conducting metal layer and being configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit, the via region comprising, within the metal layer, a distribution of removable metal selected such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.

2. The via region of claim 1, wherein the predetermined variation in the ratio of metal to nonmetal area is sufficiently low to prevent dishing when the three dimensional integrated circuit is formed.

3. The via region of claim 1, wherein the electrically conducting metal layer is a first electrically conducting metal layer and the circuit portion includes a second electrically conducting metal layer and an electrically insulating layer separating the first and second metal layers, the via region further comprising, within the second metal layer, a distribution of removable metal selected such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.

4. The via region of claim 3, further comprising at least one metal interconnect within the via region, the interconnect extending through the insulating layer between the first metal layer and the second metal layer.

5. The via region of claim 3, wherein the insulating layer is a dielectric layer.

6. The via region of claim 1, wherein the through-wafer via interconnect region is a first through-wafer via interconnect region and further comprising a second through-wafer via interconnect region located within a second circuit portion of the wafer, the second circuit portion including the metal layer and being configured for use, after dicing of the wafer, as another layer in the plurality of layers stacked vertically to form the three dimensional integrated circuit, the second via region comprising, within the metal layer, a distribution of removable metal selected such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.

7. The via region of claim 1, wherein the via region is substantially cylindrical.

8. The via region of claim 1, wherein the via region is substantially square in cross section.

9. A through-wafer via interconnect region, the via region being located within a circuit portion of a wafer, the circuit portion including a first electrically conducting metal layer, a second electrically conducting metal layer, an electrically insulating dielectric layer between the first and second metal layers, and being configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit, the via region comprising, within each of the metal layers, a distribution of removable metal selected such that the ratio of metal to nonmetal area, within the via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.

10. A method of making a through-wafer via interconnect region, comprising:

providing a wafer;

defining a circuit portion of the wafer, the circuit portion being configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit;

defining the through-wafer via interconnect region within the circuit portion;

forming an electrically conducting metal layer within the circuit portion such that removable metal in the metal layer is distributed with a ratio of metal to nonmetal area, within the via region, that varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region.

11. The method of claim 10, wherein the metal layer is formed such that the predetermined variation in the ratio of metal to nonmetal area is sufficiently low to prevent dishing when the three dimensional integrated circuit is formed.

12. The method of claim 10, wherein the electrically conducting metal layer is a first electrically conducting metal layer, further comprising:

forming a second electrically conducting metal layer within the circuit portion such that removable metal in the second metal layer is distributed with a ratio of metal to nonmetal area, within the via region, that varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region; and

forming an electrically insulating layer separating the first and second metal layers.

13. The method of claim 12, further comprising forming at least one metal interconnect within the via region, the interconnect extending through the insulating layer between the first metal layer and the second metal layer.

14. The method of claim 12, wherein forming an electrically insulating layer comprises forming a dielectric layer.

15. The method of claim 10, wherein the circuit portion of the wafer is a first circuit portion of the wafer and the through-wafer via interconnect region is a first through-wafer via interconnect region, further comprising:

defining a second circuit portion of the wafer, the second circuit portion being configured for use, after dicing of the wafer, as another layer in the plurality of layers stacked vertically to form the three dimensional integrated circuit;

defining a second through-wafer via interconnect region located within the second circuit portion of the wafer, the second via region comprising, within the metal layer, a distribution of removable metal selected such that the ratio of metal to nonmetal area, within the second via region, varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the second via region.

16. The method of claim 10, wherein defining a via region comprises defining a substantially cylindrical via region within the circuit portion.

17. The method of claim 10, wherein defining a via region comprises defining a via region, within the circuit portion, that is substantially square in cross section.

18. A method of making through-wafer via interconnect regions, comprising:

providing a wafer;

defining a first circuit portion of the wafer, the first circuit portion being configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit;

defining a first through-wafer via interconnect region within the first circuit portion;

defining a second circuit portion of the wafer, the second circuit portion being configured for use, after dicing of the wafer, as another layer in the plurality of layers stacked vertically to form a three dimensional integrated circuit;

defining a second through-wafer via interconnect region within the second circuit portion;

forming a first electrically conducting metal layer within the first and second circuit portions such that removable metal in the first metal layer is distributed with a ratio of metal to nonmetal area, within the first and second via regions, that varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the respective via regions;

forming a second electrically conducting metal layer within the first and second circuit portions such that removable metal in the second metal layer is distributed with a ratio of metal to nonmetal area, within the first and second via regions, that varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the respective via regions; and

forming an electrically insulating dielectric layer separating the first and second metal layers.

19. A method of making a circuit portion, comprising:

providing a wafer that includes a substrate;

defining a portion of the wafer as the circuit portion;

fabricating active semiconducting devices in the circuit portion;

depositing an electrically insulating layer on the substrate;

depositing an electrically conducting metal layer on the insulating layer;

fabricating a plurality of semiconducting devices in the layers; and

defining a through-wafer via interconnect region within the circuit portion,

such that the metal in the metal layer is removably distributed with a ratio of metal to nonmetal area, within the via region, that varies by less than a predetermined amount from the ratio of metal to nonmetal area outside the via region, the circuit portion being thereby configured for use, after dicing of the wafer, as one of a plurality of layers stacked vertically to form a three dimensional integrated circuit.

20. The method of claim 19, wherein the metal layer is deposited such that the predetermined variation in the ratio of metal to nonmetal area is sufficiently low to prevent dishing when the three dimensional integrated circuit is formed.

21. The method of claim 19, wherein depositing an electrically insulating layer comprises depositing a dielectric layer.

22. The method of claim 19, wherein the electrically conducting metal layer is a first electrically conducting metal layer and the electrically insulating layer is a first electrically insulating layer, further comprising:

depositing a second electrically insulating layer on the first electrically conducting metal layer;

depositing a second electrically conducting metal layer on the second insulating layer; and

depositing a third electrically insulating layer on the second electrically conducting metal layer.

23. The method of claim 22, further comprising:

forming a plurality of metal interconnects within the via region, each interconnect extending through the second insulating layer between the first metal layer and the second metal layer.

24. The method of claim 23, further comprising:

removing the third insulating layer within the via region;

removing the metal in the second metal layer within the via region;

removing the metal interconnects between the first and second metal layers;

removing the second insulating layer within the via region;

removing the metal in the first metal layer within the via region;

removing the first insulating layer within the via region;

removing the substrate within the via region;

electrically isolating the periphery of the via region; and

filling the via region with an electrically conducting metal, thereby creating a through-wafer via interconnect in the circuit portion.

25. The method of claim 24, further comprising:

dicing the wafer to separate the circuit portion, thereby rendering the circuit portion usable as a layer in a vertically stacked three dimensional integrated circuit.