POWER CONTROL SYSTEM USING A NONLINEAR DELTA-SIGMA MODULATOR WITH NONLINEAR POWER CONVERSION PROCESS MODELING

• US 20080272744A1
• Filed: 12/31/2007
• Published: 11/06/2008
• Est. Priority Date: 05/02/2007
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Melanson, John L.
• Granted Patent: US 7,719,246 B2
• Time in Patent Office: Days
• US Class Current: 323/205
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H03M 3/476 Non-linear conversion systems
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A power control system includes a switching power converter and a power factor correction (PFC) and output voltage controller. The switching power converter utilizes a nonlinear energy transfer process to provide power to a load. The PFC and output voltage controller generates a control signal to control power factor correction and voltage regulation of the switching power converter. The PFC and output voltage controller includes a nonlinear delta-sigma modulator that models the nonlinear energy transfer process of the switching power converter. The nonlinear delta-sigma modulator generates an output signal used to determine the control signal. By using the nonlinear delta-sigma modulator in a control signal generation process, the PFC and output voltage controller generates a spectrally noise shaped control signal. In at least one embodiment, noise shaping of the control signal improves power factor correction and output voltage regulation relative to conventional systems.

Claims

1. A power factor correction controller comprising:

a processor to receive and process one or more switching power converter feedback signals and generate a pulse width control signal using each processed feedback signal; and

a pulse width modulator, coupled to the signal processor, having an input to receive the pulse width control signal and generate a pulse width modulated, power factor correction (PFC) control signal to control a switch that controls a power factor correction stage of the switching power converter;

wherein a pulse width of the PFC control signal varies approximately with a square root of the PWM control signal.

2. The power factor correction stage of claim 1 wherein the processor comprises a nonlinear delta-sigma modulator that includes a quantizer, a loop filter, and a feedback path coupled between the quantizer and the loop filter, and the feedback path includes a square process that generates a square of quantizer output signals.

3. The power factor correction stage of claim 1 wherein the processor is configured to process each of the feedback signals to track a function associated with variations of a time-varying voltage input signal to the switching power converter.

4. The power factor correction stage of claim 3 wherein the PFC control signal includes a period, and the pulse width modulator is configured to modulate the period of the PFC control signal to track a function associated with variations of a time-varying voltage output signal of the switching power converter.

5. The power factor correction stage of claim 3 wherein the pulse width modulator is configured to determine a period of the PFC control signal in accordance with a root mean square of the time-varying voltage input signal to the switching power converter.

6. The power factor correction stage of claim 3 wherein the pulse width modulator is configured to modulate a period of the PFC control signal in accordance with variations in a load coupled to the switching power converter.

7. The power factor correction stage of claim 1 wherein the pulse width modulator is configured to include random modulations over time to periods of the PFC control signal.

8. The power factor correction stage of claim 1 wherein the processor is configured to process each of the feedback signals to track a function associated with variations of a time-varying output voltage of the switching power converter.

9. The power factor correction stage of claim 1 wherein the pulse width modulator is configured to generate a digital pulse width modulated power factor correction (PFC) control signal.

10. The power factor correction stage of claim 1 wherein the processor is further configured to process the one or more feedback signals of the power converter to control a period of the PFC control signal.

11. A method of controlling power factor correction of a switching power converter, the method comprising:

receiving one or more switching power converter feedback signals;

processing each received feedback signal;

generating a pulse width control signal using each processed feedback signal; and

generating a pulse width modulated, power factor correction (PFC) control signal to control a switch that controls a power factor correction stage of the switching power converter;

wherein a pulse width of the PFC control signal varies approximately with a square root of the PWM control signal.

12. The method of claim 11 wherein generating a pulse width control signal using each processed feedback signal further comprises:

generating the pulse width control signal using a nonlinear delta-sigma modulator that includes a quantizer, a loop filter, and a feedback path coupled between the quantizer and the loop filter, and the feedback path includes a square process that generates a square of quantizer output signals.

13. The method of claim 11 further comprising:

processing each of the feedback signals to track a function associated with variations of a time-varying voltage input signal to the switching power converter.

14. The method of claim 11 wherein the PFC control signal includes a period, the method further comprising:

modulating the period of the PFC control signal to track a function associated with variations of a time-varying voltage output signal of the switching power converter.

15. The method of claim 11 further comprising:

determining a period of the PFC control signal in accordance with a root mean square of the time-varying voltage input signal to the switching power converter.

16. The method of claim 11 further comprising:

modulating a period of the PFC control signal in accordance with variations in a load coupled to the switching power converter.

17. The method of claim 11 further comprising:

randomly modulating periods of the PFC control signal.

18. The method of claim 11 further comprising:

processing each of the feedback signals to track a function associated with variations of a time-varying output voltage of the switching power converter.

19. The method of claim 11 further comprising:

generating a digital pulse width modulated power factor correction (PFC) control signal.

20. The method of claim 11 further comprising:

processing the one or more feedback signals of the power converter to control a period of the PFC control signal.

21. An apparatus to control power factor correction of a switching power converter, the apparatus comprising:

means for receiving one or more switching power converter feedback signals;

means for generating a pulse width control signal using each processed feedback signal; and

means for generating a pulse width modulated, power factor correction (PFC) control signal to control a switch that controls a power factor correction stage of the switching power converter;

wherein a pulse width of the PFC control signal varies approximately with a square root of the PWM control signal.