Power Factor Correction (PFC) Controller and Method Using a Finite State Machine to Adjust the Duty Cycle of a PWM Control Signal

• US 20080272748A1
• Filed: 04/22/2008
• Published: 11/06/2008
• Est. Priority Date: 05/02/2007
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Melanson, John Laurence
• Granted Patent: US 7,821,237 B2
• Time in Patent Office: Days
• US Class Current: 323/207
• CPC Class Codes: H02M 1/4225 using a non-isolated boost converter
• CPC Class Codes: H03M 3/476 Non-linear conversion systems
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
• CPC Class Codes: Y02P 80/10 Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier

Abstract

A power factor correction (PFC) controller and method uses a finite state machine to adjust the duty cycle of a pulse width modulation (PWM) switching control signal. The PFC controller has a target current generator that receives the link output voltage and generates a target current proportionate to the rectified line input voltage. The PFC controller further includes a comparator which outputs a two-level current comparison result signal. The finite state machine responsive to the two-level current comparison result signal, generates a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

Claims

1. A power factor corrector (PFC), comprising:

a switch-mode boost stage having a switch and an inductor coupled to the switch wherein the switch-mode boost stage receives a rectified line input voltage and provides a link output voltage and wherein a sensed current is observed from the switch-mode boost stage; and

a target current generator for receiving the link output voltage and for generating a target current proportionate to the rectified line input voltage;

a comparator for receiving a target current value representative of the target current and a sensed current value representative of the sensed current and outputting a two-level current comparison result signal; and

a finite state machine responsive to the two-level current comparison result signal, generating a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

2. The PFC of claim 1, wherein the sensed current is a switch current of the switch.

3. The PFC of claim 2 wherein the finite state machine generates the switch control signal such that the switch current is greater than the target current during approximately fifty percent of an on-time duration of the switch and less than the target current during a remaining approximately fifty percent of the on-time duration of the switch.

4. The PFC of claim 1 wherein the sensed current is a boost inductor current in the inductor.

5. The PFC of claim 4 wherein the finite slate machine generates the switch control signal such that the boost inductor current is greater than the target current during approximately fifty percent of an on-time duration of the switch and less than the target current during a remaining approximately fifty percent of the on-time duration of the switch.

6. The PFC of claim 1 further comprising a timer which is utilized by the finite state machine for measuring a below-time duration in which the sensed current is less than the target current and adjusting the duly cycle of the switch control signal in conformity with the below-time duration.

7. The PFC of claim 6 further comprising a time duration generator which receives a signal representative of the rectified line input voltage and adjusts an off-time duration of the switch in conformity with the below-time duration.

8. The PFC of claim 7 further comprising a detector for detecting a RMS voltage of the line input voltage and wherein the time duration generator receives and uses the RMS voltage to responsively determine the off-time duration.

9. The PFC of claim 7 wherein a power level is detected from the link output voltage and wherein the time duration generator receives and uses the power level to responsively determine the off-time duration.

10. The PFC of claim 6 further comprising a time duration generator which receives a signal representative of the rectified line input voltage and adjusts a switching period for the switch in conformity with the below-time duration.

11. The PFC of claim 10 further comprising a detector for detecting a RMS voltage of the line input voltage and wherein the time duration generator receives and uses the RMS voltage to responsively determine the switching period.

12. The PFC of claim 10 wherein a power level is detected from the link output voltage and wherein the time duration generator receives and uses the power level to responsively determine the switching period.

13. The PFC of claim 6 wherein the finite state machine calculates an on-time duration based on a recurrence relation responsive to a prior on-time duration and the below-time duration.

14. The PFC of claim 6 wherein the timer further comprises:

an oscillator; and

a digital counter that counts responsively to the oscillator and the two-level current comparison result signal; and

wherein the switch control signal controls the switch in response to the digital counter.

15. The PFC of claim 1 wherein the target current generator, the comparator, and the finite state machine are incorporated into a single integrated circuit.

16. The PFC of claim 15 wherein the integrated circuit further comprises a timer that includes an oscillator and a counter.

17. A method for power factor correction (PFC), comprising:

coupling a switch and an inductor together to form a switch-mode boost stage that receives a rectified line input voltage and provides a link output voltage;

observing a sensed current from the switch-mode boost stage;

receiving a link output voltage;

generating a target current proportionate to the rectified line input voltage;

comparing a target current value representative of the target current and a sensed current value representative of the sensed current;

in response to the comparing, outputting a two-level current comparison result signal; and

in response to the two-level current comparison result signal, generating a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

18. The method of claim 17, wherein sensing a sensed current from the switch-mode boost stage further comprises:

sensing a switch current of the switch.

19. The method of claim 18 wherein generating a switch control signal further comprises:

generating the switch control signal such that the switch current is greater than the target current during approximately fifty percent of an on-time duration of the switch and less than the target current during a remaining approximately fifty percent of the on-time duration of the switch.

20. The method of claim 17 wherein sensing a sensed current from the switch-mode boost stage further comprises:

sensing a boost inductor current in the inductor.

21. The method of claim 20 wherein generating a switch control signal further comprises:

generating the switch control signal such that the boost inductor current is greater than the target current during approximately fifty percent of an on-time duration of the switch and less than the target current during a remaining approximately fifty percent of the on-time duration of the switch.

22. The method of claim 17 further comprising:

measuring a below-time duration in which the sensed current is less than the target current; and

adjusting an on-time duration of a switching time period for the switch in conformity with the below-time duration.

23. The method of claim 22 further comprising:

adjusting an off-time duration of the switch in conformity with the below-time duration.

24. The method of claim 22 further comprising:

adjusting a switching period for the switch in conformity with the below-time duration.

25. The method of claim 22 further comprising:

calculating an on-time duration of the switch based on a recurrence relation responsive to a prior on-time duration and the below-time duration.

26. An integrated circuit which incorporates a power factor correction controller that includes a target current generator, a comparator, and a finite state machine, the integrated circuit configured to:

receive a signal representative of a rectified line input voltage;

observe a sensed current from an external switch-mode boost stage;

receive another signal representative of a link output voltage;

generate a target current proportionate to the input signal;

compare a target current value representative of the target current and a sensed current value representative of the sensed current;

in response to the compare, output a two-level current comparison result signal; and

in response to the two-level current comparison result signal, generate a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

27. A power factor corrector (PFC), comprising:

a switch-mode boost stage having a switch and an inductor coupled to the switch wherein the switch-mode boost stage receives a rectified line input voltage and provides a link output voltage and wherein a sensed current is observed from the switch-mode boost stage; and

a target current generator for receiving the link output voltage and for generating a target current proportionate to the rectified line input voltage;

a ripple current estimator for generating a ripple current that estimates a peak-to-peak inductor ripple current;

a comparator, responsive to the target current, the ripple current, and the sensed current, for outputting a two-level current comparison result signal; and

a finite slate machine responsive to the two-level current comparison result signal, generating a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

28. The PFC of claim 27, wherein the finite state machine turns on the switch for an on-time duration starting when the sensed current is less than a sum of the target current and half of the ripple current and the finite state machine turns off the switch for an off-time duration starting when the sensed current is greater than or equal to a sum of the target current and half of the ripple current.

29. The PFC of claim 27 wherein the off-time duration is adjusted in conformity with the ripple current.

30. The PFC of claim 27 further comprising a timer that includes an oscillator and a counter wherein the timer is utilized by the finite state machine to measure an on-time duration and an off-time duration of the switch.

31. The PFC of claim 27 wherein the target current generator, the comparator, and the finite state machine are incorporated into a single integrated circuit.

32. A method for power factor correction (PFC), comprising:

coupling a switch and an inductor together to form a switch-mode boost stage that receives a rectified line input voltage;

observing a sensed current from the switch-mode boost stage;

receiving a link output voltage;

generating a target current proportionate to the rectified line input voltage;

generating a ripple current that estimates a peak-to-peak inductor ripple current;

in response to the target current, the ripple current, and the sensed current, generating a two-level current comparison result signal; and

in response to the two-level current comparison result signal, generating a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.

33. The method of claim 32, wherein generating a switch control signal further comprises:

turning on the switch for an on-time duration starting when the sensed current is less than a sum of the target current and half of the ripple current; and

turning off the switch for an off-time duration starting when the sensed current is greater than or equal to a sum of the target current and half of the ripple current.

34. The method of claim 33 further comprising:

adjusting the off-time duration in conformity with the ripple current.

35. An integrated circuit which incorporates a power factor correction controller that includes a target current generator, a comparator, and a finite state machine, the integrated circuit configured to:

receive a signal representative of a rectified line input voltage;

observe a sensed current from an external switch-mode boost stage;

receive another signal representative of a link output voltage;

generate a target current proportionate to the rectified line input voltage;

generate a ripple current that estimates a peak-to-peak inductor ripple current;

in response to the target current, the ripple current, and the sensed current, generate a two-level current comparison result signal; and

in response to the two-level current comparison result signal, generate a switch control signal that has a duty cycle which is adjusted for controlling the switch so that the sensed current is approximately proportionate to the rectified line input voltage, such that power factor correction is performed.