"Interleaved Three-Dimensional On-Chip Differential Inductors and Transformers

• US 20080272875A1
• Filed: 08/02/2006
• Published: 11/06/2008
• Est. Priority Date: 08/04/2005
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Chang, Mau-Chung Frank, Huang, Daquan
• Granted Patent: US 8,325,001 B2
• Time in Patent Office: Days
• US Class Current: 336/182
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor

Abstract

Interleaved three-dimensional (3D) on-chip differential inductors 110, 120 and transformer 100 are disclosed. The interleaved 3D on-chip differential inductors 110, 120 and transformer 100 make the best use of multiple metal layers in mainstream standard processes, such as CMOS, BiCMOS and SiGe technologies.

Claims

1. An inductive 3D on-chip apparatus comprising a first coil and a second coil, the first and second coils each comprising successively connected windings centered on a common axis, wherein the windings of the first coil are interleaved with the windings of the second coil.

2. The inductive 3D on-chip apparatus according to claim 1 wherein the windings of the first coil are not aligned in the direction of the common axis with adjacent windings of the second coil.

3. The inductive 3D on-chip apparatus according to claim 1 wherein the first coil and the second coil each have a first end and a second end, the second end of the first coil and the second end of the second coil being connected to a first center tap, the first end of the first coil is a first port and the first end of the second coil is a second port.

4. The inductive 3D on-chip apparatus according to claim 3 wherein the apparatus is an interleaved three dimensional on-chip differential inductor.

5. The inductive 3D on-chip apparatus according to claim 1 further comprising third and fourth coils, the third and fourth coils comprising successively connected windings centered on the common axis, wherein the windings of the third coil are interleaved with the windings of the fourth coil, the third coil and the fourth coil each have a first end and a second end, the second end of the third coil and the second end of the fourth coil being connected to a second center tap, and the first end of the third coil is a third port and the first end of the fourth coil is a fourth port.

6. The inductive 3D on-chip apparatus according to claim 5 wherein the windings of the first coil are not aligned in the direction of the common axis with adjacent windings of the second coil.

7. The inductive 3D on-chip apparatus according to claim 6 wherein the windings of the third coil are not aligned in the direction of the common axis with adjacent windings of the fourth coil.

8. The inductive 3D on-chip apparatus according to claim 5 wherein the apparatus is an interleaved three dimensional on-chip transformer.

9. The inductive 3D on-chip apparatus according to claim 5 wherein the first center tap is a fifth port and the second center tap is a sixth port.

10. The inductive 3D on-chip apparatus according to claim 5 wherein the first and second center taps are connected to form a fifth port.

11. The inductive 3D on-chip apparatus according to claim 3 further comprising a variable capacitor operatively connected in parallel with the first and second ports.

12. The inductive 3D on-chip apparatus according to claim 5 further comprising a variable capacitor operatively connected in parallel with the first and second ports.

13. The inductive 3D on-chip apparatus according to claim 12 further comprising a variable capacitor operatively connected in parallel with the third and fourth ports.

14. An interleaved three dimensional on-chip differential inductor, comprising;

first and second coils formed on a plurality of layers on a chip and sharing a common alignment axis, each of the first and second coils comprising a plurality of partial windings wherein each partial winding is disposed on a layer with connections between successive partial windings of each of the first and second coils passing through the layers; and

wherein the partial windings of the first and second coils are generally perpendicular to the common alignment axis and are interleaved.

15. The interleaved three dimensional on-chip differential inductor according to claim 14 wherein each partial winding of the first coil is disposed on a layer with a partial winding of the second coil.

16. The interleaved three dimensional on-chip differential inductor according to claim 15 wherein each partial winding disposed on a layer defines part of the shape of a simple polygon or a simple closed curve.

17. The interleaved three dimensional on-chip differential inductor according to claim 16 wherein the partial winding of the first coil and the partial winding of the second coil disposed on a layer generally define the shape of a simple polygon or a simple closed curve.

18. The interleaved three dimensional on-chip differential inductor according to claim 17 wherein the area of the simple polygon or a simple closed curve defined by the partial windings on a layer is larger or smaller than the area of the simple polygon or a simple closed curve defined by the partial windings on adjacent layers.

19. The interleaved three dimensional on-chip differential inductor according to claim 14 wherein the connections between successive partial windings of a coil are vias.

20. The inductive 3D on-chip differential inductor according to claim 14 in which the first coil and the second coil each have a first end and a second end, the second end of the first coil and the second end of the second coil being connected to a center tap, the first end of the first coil is a first port and the first end of the second coil is a second port.

21. An interleaved three dimensional on-chip transformer, comprising;

first and second coils formed on a plurality of layers on a chip and sharing a common alignment axis, each of the first and second coils comprising a plurality of partial windings wherein each partial winding is disposed on a layer with connections between successive partial windings of each of the first and second coils passing through the layers separating the successive partial windings of each of the first and second coils;

wherein the partial windings of the first and second coils are generally perpendicular to the common alignment axis and are interleaved;

third and fourth coils formed on the plurality of layers of the chip and sharing the common alignment axis, each of the third and fourth coils comprising a plurality of partial windings wherein each partial winding is disposed on a layer with connections between successive partial windings of each of the third and fourth coils passing through the layers separating the successive windings of each of the third and fourth coils; and

wherein the partial windings of the third and fourth coils are generally perpendicular to the common alignment axis and are interleaved.

22. The interleaved three dimensional on-chip transformer according to claim 21 wherein a partial winding of the first coil is disposed on a layer with a partial winding of the second coil.

23. The interleaved three dimensional on-chip transformer according to claim 22 wherein partial windings of the first, second, third, and fourth coils are disposed on at least one layer.

24. The interleaved three dimensional on-chip transformer according to claim 22 wherein partial windings of the first, second, third, and fourth coils are disposed on each of the layers having partial windings disposed thereon.

25. The interleaved three dimensional on-chip transformer according to claim 22 wherein a partial winding of the third coil is disposed on a layer with a partial winding of the fourth coil.

26. The interleaved three dimensional on-chip transformer according to claim 25 wherein the partial windings of the first and second coils and the partial windings of the third and fourth coils are disposed on alternate layers.

27. The interleaved three dimensional on-chip transformer according to claim 21 wherein each partial winding disposed on a layer defines part of the shape of a simple polygon or a simple closed curve.

28. The interleaved three dimensional on-chip transformer according to claim 21 wherein the partial winding of the first coil and the partial winding of the second coil disposed on a layer generally define the shape of a simple polygon or a simple closed curve.

29. The interleaved three dimensional on-chip transformer according to claim 28 wherein the partial winding of the third coil and the partial winding of the fourth coil disposed on a layer generally define the shape of a simple polygon or a simple closed curve.

30. The interleaved three dimensional on-chip transformer according to claim 29 wherein the area of the simple polygon or a simple closed curve defined by the partial windings of the first coil and second coils on a layer is larger or smaller than the area of the simple polygon or a simple closed curve defined by the nearest partial windings of the first and second coils.

31. The interleaved three dimensional on-chip transformer according to claim 29 wherein the area of the simple polygon or a simple dosed curve defined by the partial windings of the third coil and fourth coils on a layer is larger or smaller than the area of the simple polygon or a simple closed curve defined by the nearest partial windings of the third and fourth coils.

32. The interleaved three dimensional on-chip transformer according to claim 21 wherein the connections between successive partial windings of a coil are vias.

33. The interleaved 3D on-chip transformer according to claim 21 wherein the first coil and the second coil each have a first end and a second end, the second end of the first coil and the second end of the second coil being connected to a first center tap, the first end of the first coil is a first port and the first end of the second coil is a second port, the third coil and the fourth coil each have a first end and a second end, the second end of the third coil and the second end of the fourth coil being connected to a second center tap, the first end of the third coil is a third port and the first end of the fourth coil is a second port.

34. The interleaved 3D on-chip transformer according to claim 33 wherein the first center tap is a fifth port and the second center tap is a sixth port.

35. The interleaved 3D on-chip transformer according to claim 33 wherein the first center tap and the second center tap are connected to be a fifth port.

36. A method for making three-dimensional on-chip differential inductors and transformers, comprising:

forming a substrate in successive layers on a chip;

disposing two partial windings on each layer, the partial windings having a common axis and forming the shape of a simple polygon or a simple closed curve;

connecting each of the partial windings disposed on one of the layers to one of the partial windings of an adjacent layer;

wherein the partial windings of one layer are disposed so as to be interleaved with the partial windings of adjacent layers.

37. The method for making three-dimensional on-chip differential inductors and transformers according to claim 36 in which the step of disposing partial windings on each layer comprises disposing four partial windings on each layer, the partial windings having a common axis and being arranged in pairs of partial windings wherein each pair of partial windings forms the shape of a simple polygon or a simple closed curve.