SYMMETRIC DIFFERENTIAL CURRENT SENSE AMPLIFIER

• US 20080273394A1
• Filed: 05/02/2007
• Published: 11/06/2008
• Est. Priority Date: 05/02/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kern, Thomas
• Granted Patent: US 7,800,968 B2
• Time in Patent Office: Days
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell. The differential current integrating sense amplifier is also used for instrumentation, communication, data storage, sensing, biomedical device, and analog to digital conversion.

Claims

1. A differential sense amplifier, comprising:

a first circuit operable to integrate the current from an input;

a second circuit operable to integrate a reference current signal; and

a comparator operable to compare the voltages of the first integrator circuit and the second integrator circuit, thereby indicating whether the current from the input or the reference current signal is greater.

2. The differential sense amplifier of claim 1, wherein the first circuit comprises a current mirror operable to sense a current from the input and mirror the input current signal to an integrator.

3. The differential sense amplifier of claim 1, wherein the second circuit comprises a current mirror operable to sense the reference current signal and mirror the reference current signal to an integrator.

4. The differential sense amplifier of claim 1, wherein the differential sense amplifier comprises a memory cell sense amplifier, the input comprises a current signal from a memory cell, and the reference current signal comprises a current signal from a reference memory cell.

5. The differential sense amplifier of claim 1, further comprising an equalizer operable to bring a first circuit integrator capacitor comprising a part of the first circuit and a second circuit integrator capacitor comprising a part of the second circuit to the same charge state.

6. The differential sense amplifier of claim 1, wherein a first circuit integrator capacitor comprising a part of the first circuit and a second circuit integrator capacitor comprising a part of the second circuit are substantially matched.

7. The differential sense amplifier of claim 1, wherein the differential sense amplifier comprises a part of at least one of a sensor, an instrumentation device, a communications systems, a data storage device, a biomedical device, and an analog-to-digital converter.

8. A method of operating a differential sense amplifier, comprising:

receiving in a first circuit an input current;

integrating the input current to produce an accumulated input voltage;

receiving in a second circuit a reference current;

integrating the reference current to produce an accumulated reference voltage; and

comparing the accumulated input voltage with the accumulated reference voltage to determine whether the input current is greater or smaller than the reference current.

9. The method of operating a differential sense amplifier of claim 8, further comprising mirroring the received input current to an integrator comprising a part of the first circuit.

10. The method of operating a differential sense amplifier of claim 8, further comprising mirroring the received reference current to an integrator comprising a part of the second circuit.

11. The method of operating a differential sense amplifier of claim 8, wherein the input current comprises a memory cell current and the reference current comprises a reference threshold current.

12. The method of operating a differential sense amplifier of claim 11, wherein the reference threshold current is the current flowing through a reference memory cell.

13. The method of operating a differential sense amplifier of claim 8, further comprising equalizing the charge on a first capacitor used for integrating the input current in the first circuit with the charge on a second capacitor used for integrating the reference current in the second circuit.

14. The method of operating a differential sense amplifier of claim 8, wherein the comparing occurs less than four nanoseconds after receiving the input current and the reference current signals.

15. A memory device, comprising:

an array of nonvolatile memory cells;

an output buffer; and

a differential integrating sense amplifier linking the array of nonvolatile memory cells to the output buffer.

16. The memory device of claim 15, wherein the differential integrating sense amplifier comprises:

a first circuit operable to integrate the current from a memory cell being read;

a second circuit operable to integrate a threshold reference current signal; and

a comparator operable to compare the voltages of the first integrator circuit and the second integrator circuit, thereby indicating whether the current from the memory cell being read or the threshold reference current signal is greater.

17. The memory device of claim 16, wherein the first circuit comprises a current mirror operable to sense a current from the memory cell being read and mirror the memory cell current signal to an integrator.

18. The memory device of claim 16, wherein the second circuit comprises a current mirror operable to sense the threshold reference current signal and mirror the threshold reference current signal to an integrator operable to integrate the threshold reference current signal in the second circuit.

19. The memory device of claim 16, further comprising an equalizer operable to bring a first circuit integrator capacitor comprising a part of the first circuit and a second circuit integrator capacitor comprising a part of the second circuit to the same charge state.

20. The memory device of claim 16, wherein a first circuit integrator capacitor comprising a part of the first circuit and a second circuit integrator capacitor comprising a part of the second circuit are substantially matched.