METHOD OF MAKING HIGH EFFICIENCY UV VLED ON METAL SUBSTRATE

• US 20080274572A1
• Filed: 05/04/2007
• Published: 11/06/2008
• Est. Priority Date: 05/04/2007
• Status: Active Grant

• Current Assignee: Semileds Optoelectronics Company Limited (SemiLEDs Inc)
• Original Assignee: Semileds Optoelectronics Company Limited (SemiLEDs Inc)
• Inventors: TRAN, CHUONG ANH
• Granted Patent: US 7,759,146 B2
• Time in Patent Office: Days
• US Class Current: 438/29
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate

Abstract

A method of fabricating ultraviolet (UV) vertical light-emitting diode (VLED) structures composed of AlInGaN or AlGaN with increased crystalline quality and a faster growth rate when compared to conventional AlInGaN or AlGaN LED structures is provided. This may be accomplished by forming a sacrificial GaN layer above a carrier substrate, and then depositing the light-emitting diode (LED) stack above the sacrificial GaN layer. The sacrificial GaN layer may then be removed in subsequent processing steps.

Claims

1. A method of fabricating a vertical light-emitting diode (VLED) structure, comprising:

growing a sacrificial GaN layer above a sapphire substrate;

forming a light-emitting diode (LED) stack comprising at least one of AlInGaN and AlGaN above the sacrificial GaN layer;

depositing one or more layers of a metal substrate above the LED stack;

removing the sapphire substrate; and

removing the sacrificial GaN layer.

2. The method of claim 1, wherein the sacrificial GaN layer comprises an n-doped, an undoped, or a p-doped GaN layer.

3. The method of claim 1, wherein the sacrificial GaN layer is doped with at least one of magnesium, silicon, and zinc.

4. The method of claim 1, wherein the sacrificial GaN layer has a thickness between 10 nm and 10 μ

m.

5. The method of claim 1, wherein a layer of the LED stack adjacent to the sacrificial GaN layer is an undoped layer.

6. The method of claim 1, wherein the metal substrate comprises at least one of Cu, Ni, Au, Ag, Co, Pd, Pt, W, Cr, Ti, or alloys thereof.

7. The method of claim 1, wherein the metal substrate comprises more than one layer.

8. The method of claim 1, wherein the metal substrate has a thickness greater than 25 μ

m.

9. The method of claim 1, wherein depositing the one or more layers of the metal substrate comprises at least one of electrochemical deposition (ECD), electroless chemical deposition (ElessCD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), evaporation, or a plasma spray technique.

10. The method of claim 1, further comprising disposing a reflective layer between the LED stack and the metal substrate.

11. The method of claim 10, further comprising disposing a conductive transparent layer between the LED stack and the reflective layer.

12. The method of claim 1, wherein removing the sapphire substrate comprises at least one of pulsed laser irradiation, chemical mechanical polishing (CMP), wet etching, and selected photoenhanced chemical etching.

13. The method of claim 1, wherein removing the sacrificial GaN layer comprises at least one of wet etching, dry etching, mechanical polishing, and chemical mechanical polishing (CMP).

14. The method of claim 1, further comprising forming an electrode coupled to the exposed LED stack after removing the sacrificial GaN layer.

15. A method of fabricating a vertical light-emitting diode (VLED) structure, comprising:

growing a sacrificial GaN layer above a sapphire substrate;

forming an n-doped layer above the sacrificial GaN layer;

forming an active layer above the n-doped layer;

forming a p-doped layer above the active layer, wherein the n-doped layer, the active layer, and the p-doped layer comprise at least one of AlInGaN and AlGaN above the sacrificial GaN layer;

depositing one or more layers of a metal substrate above the p-doped layer;

removing the sapphire substrate; and

removing the sacrificial GaN layer.

16. The method of claim 15, wherein the sacrificial GaN layer comprises an n-doped, an undoped, or a p-doped GaN layer.

17. The method of claim 15, wherein the sacrificial GaN layer is doped with at least one of magnesium, silicon, and zinc.

18. The method of claim 15, wherein the sacrificial GaN layer has a thickness between 10 nm and 10 μ

m.

19. The method of claim 15, wherein the metal substrate comprises at least one of Cu, Ni, Au, Ag, Co, Pd, Pt, W, Cr, Ti, or alloys thereof.

20. The method of claim 15, wherein depositing the one or more layers of the metal substrate comprises at least one of electrochemical deposition (ECD), electroless chemical deposition (ElessCD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), evaporation, and a plasma spray technique.

21. The method of claim 15, further comprising disposing a reflective layer between the p-doped layer and the metal substrate.

22. The method of claim 21, further comprising disposing a conductive transparent layer between the p-doped layer and the reflective layer.

23. The method of claim 15, wherein removing the sacrificial GaN layer comprises at least one of wet etching, dry etching, mechanical polishing, and chemical mechanical polishing (CMP).

24. The method of claim 15, wherein neither the p-doped layer nor the n-doped layer comprises GaN.