WIRELESS COMMUNICATION MODULES

• US 20080274630A1
• Filed: 05/02/2008
• Published: 11/06/2008
• Est. Priority Date: 05/02/2007
• Status: Active Grant

• Current Assignee: Synapse Wireless Incorporated (Mcwane Incorporated)
• Original Assignee: Synapse Wireless Incorporated (Mcwane Incorporated)
• Inventors: Watson, Thomas J., Phillips, Terry G., Shelton, Gary W.
• Granted Patent: US 8,009,437 B2
• Time in Patent Office: Days
• US Class Current: 439/74
• CPC Class Codes: G01D 21/00 Measuring or testing not otherwise provided for
• CPC Class Codes: H04L 67/12 specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks

Abstract

The present disclosure generally pertains to wireless communication modules that can be used for enabling wireless communication in various applications. A wireless communication module in accordance with one embodiment may be interfaced with other devices, such as nodes of a wireless sensor network (WSN). The module has rows of male integrated circuit (IC) pins that may be interfaced with female pin receptacles of another device. The module receives wireless signals and provides the data of such wireless signals to the other device. The module also receives data from the other devices and packetizes such data for wireless communication.

Claims

1. A wireless communication module, comprising:

a first printed circuit board (PCB);

a first row of conductive pins for interfacing with a female connector on a second PCB of a network node, the first row of conductive pins extending from a side of the PCB;

a second row of conductive pins for interfacing with a female connector on the second PCB, the second row of conductive pins extending from the side of the PCB; and

circuitry residing on the first PCB, the circuitry configured to receive a first plurality of data packets transmitted over a wireless network, the circuitry configured to depacketize the first plurality of data packets thereby recovering a first set of data, the circuitry further configured to transmit the first set of data, via at least one of the pin of the first or second row, to circuitry residing on the second PCB,

wherein the first row is substantially parallel to the second row, wherein a separation distance between pin centers of the first row and pin centers of the second row is about 1.29 inches, and wherein a distance from a center of a pin of the first row to a center of an adjacent pin of the first row is about 0.08 inches.

2. The module of claim 1, wherein each pin of the first row has a center that is about 0.08 inches from a center of a respective pin of the first row, and wherein each pin of the second row has a center that is about 0.08 inches from a center of a respective pin of the second row.

3. The module of claim 1, wherein the first and second rows are substantially parallel to a first axis, and wherein each of the pins of the first row is aligned with a respective pin of the second row along a second axis that is perpendicular to the first axis.

4. The module of claim 1, further comprising an analog-to-digital (A/D) converter, wherein the first row has an analog pin coupled to the A/D converter, and wherein the second row has a power supply pin positioned adjacent to the analog pin.

5. The module of claim 4, further comprising an antenna residing on the PCB.

6. The module of claim 4, wherein a center of the power supply pin is about 0.08 inches from a center of the analog pin.

7. The module of claim 4, wherein the first and second rows are substantially parallel to a first axis, and wherein the first row has a plurality of serial input/output (I/O) pins, one of the serial I/O pins substantially aligned with the analog pin of the second row along a second axis that is perpendicular to the first axis.

8. The module of claim 1, wherein the first row has a plurality of serial input/output (I/O) pins, wherein the second row has a power supply pin, wherein the first and second rows are substantially parallel to a first axis, and wherein a pin adjacent one of the serial I/O pins is aligned with the power supply pin of the second row along a second axis that is perpendicular to the first axis.

9. The module of claim 1, wherein the first PCB has a first hole and a second hole, a center of the first hole separated from a center of the second hole by about 0.98 inches.

10. The module of claim 1, wherein the circuitry residing on the first PCB is further configured to receive a second set of data from the network node via at least one of the pins of the first or second row, the circuitry residing on the first PCB further configured to packetize the second set of data into a second plurality of data packets and to transmit the second plurality of data packets over the wireless network.

11. The module of claim 1, wherein the each of the pins of the first and second rows is inserted into a respective receptacle of a sensor node in a wireless sensor network.

12. A node for use in a wireless sensor network, comprising:

a wireless communication module having a first printed circuit board (PCB), a first row of conductive pins extending from the first PCB, a second row of conductive pins extending from the first PCB, and first circuitry residing on the first PCB, wherein the first row is substantially parallel to the second row, wherein a separation distance between pin centers of the first row and pin centers of the second row is about 1.29 inches, and wherein a distance from a center of a pin of the first row to a center of an adjacent pin of the first row is about 0.08 inches;

a second PCB;

a first row of receptacles residing on the second PCB and receiving the first row of pins;

a second row of receptacles residing on the second PCB and receiving the second row of pins; and

second circuitry residing on the second PCB, the second circuitry comprising a power supply coupled to a power supply pin of the second row of conductive pins, the first and second circuitry configured to communicate data serially via a plurality of serial input/output (I/O) pins of the first row of conductive pins, wherein the first and second rows of conductive pins are substantially parallel to a first axis, and wherein one of the serial I/O pins is substantially aligned with a pin of the second row of conductive pins along a second axis that is perpendicular to the first axis, and wherein the power supply pin is adjacent to the pin substantially aligned with the one I/O pin,

wherein the first circuitry is configured to receive a first plurality of data packets and to depacketize the first plurality of data packets thereby recovering a first set of data, the first circuitry configured to transmit the first set of data to the second circuitry via the serial I/O pins.

13. The node of claim 12, wherein each pin of the first row of conductive pins has a center that is about 0.08 inches from a center of a respective pin of the first row of conductive pins, and wherein each pin of the second row of conductive pins has a center that is about 0.08 inches from a center of a respective pin of the second row of conductive pins.

14. The node of claim 12, wherein the first and second rows of conductive pins are substantially parallel to a first axis, and wherein each of the pins of the first row of conductive pins is substantially aligned with a respective pin of the second row of conductive pins along a second axis that is perpendicular to the first axis.

15. The node of claim 12, further comprising an antenna residing on the first PCB.

16. The node of claim 12, wherein a center of the power supply pin is about 0.08 inches from a center of the pin that is substantially aligned with the one serial I/O pin.

17. The node of claim 12, further comprising an analog-to-digital (A/D) converter, wherein the second row of conductive pins has an analog pin coupled to the A/D converter.

18. The node of claim 17, wherein the first and second rows of conductive pins are substantially parallel to a first axis, and wherein one of the serial I/O pins of the first row of conductive pins is substantially aligned with the analog pin of the second row along a second axis that is perpendicular to the first axis.

19. The node of claim 12, wherein the first PCB has a first hole and a second hole, a center of the first hole separated from a center of the second hole by about 0.98 inches.

20. The node of claim 12, wherein the second circuitry is configured to transmit a second set of data to the first circuitry via the serial I/O pins, and wherein the first circuitry is configured to packetize the second set of data into a second plurality of data packets and to transmit the second plurality of data packets.

21. The node of claim 12, wherein one of the rows of receptacles has an end receptacle at an end of the one row, wherein one of the rows of conductive pins has a power supply pin inserted into the end receptacle.

22. A node for use in a wireless sensor network, comprising:

a wireless communication module having a first printed circuit board (PCB), a first row of conductive pins extending from the first PCB, a second row of conductive pins extending from the first PCB, and first circuitry residing on the first PCB, wherein the first row is substantially parallel to the second row, wherein a separation distance between pin centers of the first row and pin centers of the second row is about 1.29 inches, and wherein a distance from a center of a pin of the first row to a center of an adjacent pin of the first row is about 0.08 inches;

a second PCB;

a first row of receptacles residing on the second PCB and receiving the first row of conductive pins;

a second row of receptacles residing on the second PCB and receiving the second row of conductive pins; and

second circuitry residing on the second PCB, one of the first or second rows of receptacles having an end and a receptacle positioned adjacent to the end, the sensor node having a power supply coupled to one of the pins of the first or second row of conductive pins, the one pin inserted into the receptacle positioned adjacent to the end,

wherein the first circuitry is configured to receive a first plurality of data packets and to depacketize the first plurality of data packets thereby recovering a first set of data, the first circuitry configured to transmit the first set of data to the second circuitry via at least one pin of the first or second row of conductive pins.