Adaptive-Allocation Of I/O Bandwidth Using A Configurable Interconnect Topology

• US 20080276020A1
• Filed: 07/22/2008
• Published: 11/06/2008
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ching, Michael, Woo, Steven
• Granted Patent: US 8,073,009 B2
• Time in Patent Office: Days
• US Class Current: 710/106
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0294 Provision for current-mode coupling
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04L 5/143 for modulated signals H04L5/1469 takes precedence
• CPC Class Codes: H04L 5/18 Automatic changing of the traffic direction
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention.

Claims

1. An integrated circuit comprising:

an interface including a first and second portion; and

a register to store a value that indicates at least one of a first and second mode of operation, wherein

during the first mode of operation, the first and second interface portions transmit and receive signals, and

during the second mode of operation, the first interface portion transmits unidirectional signals and the second interface portion receives unidirectional signals.

2. The integrated circuit of claim 1 comprising:

a control circuit to output the value in response to a number of times the first interface portion transitions between transmitting signals and receiving signals during a period of time.

3. The integrated circuit of claim 1 comprising:

a control circuit to output the value in response to a number of transmit commands received at the interface.

4. The integrated circuit of claim 1 comprising:

a control circuit to output the value in response to a number of receive commands received at the interface.

5. The integrated circuit of claim 1 comprising:

a control circuit to output the value during initialization.

6. The integrated circuit of claim 1 comprising:

a control circuit to output the value during typical operation.

7. The integrated circuit of claim 1 comprising:

a control circuit to output the value in response to a priority of data to be transferred.

8. The integrated circuit of claim 1 comprising:

a control circuit to output the value in response to executable instructions.

9. The integrated circuit of claim 1 comprising:

a control circuit to output the value in response to an average time a data packet waits to be transmitted.

10. The integrated circuit of claim 1 comprising:

a control circuit to output the value in response to an amount of power consumption of the integrated circuit.

11. The integrated circuit of claim 1 comprising:

a control circuit to output the value in response to a temperature of the integrated circuit.

12. The integrated circuit of claim 1 comprising:

a control circuit to output the value in response to a signal that indicates a requested bandwidth.

13. The integrated circuit of claim 1 wherein the integrated circuit is operable in a third mode of operation and wherein the register stores a value that indicates at least one of the first, second and third mode of operation, wherein

during the third mode of operation, the first interface portion transmits and receives signals and the second interface portion is disabled to transmit and receive signals.

14. The integrated circuit of claim 13 wherein the third mode of operation is a phase calibration mode.

15. The integrated circuit of claim 13 wherein the third mode of operation is an impedance calibration mode.

17. The integrated circuit of claim 1 wherein the measured value is selected from power consumption of the integrated circuit, temperature of the integrated circuit, number of data packets to be transmitted, number of data packets to be received, number of transmit commands, number of receive commands, average time a data packet waits to be transmitted and bandwidth request.

16. An integrated circuit comprising:

an interface including a first and second portion;

a register to store a value that indicates at least one of a first and second mode of operation; and

a control circuit to output the value in response to a comparison of a measured value and a threshold value, wherein

during the first mode of operation, the first and second interface portions transmit and receive signals, and

during the second mode of operation, the first interface portion transmits unidirectional signals and the second interface portion receives unidirectional signals.

18. The integrated circuit of claim 16 wherein the integrated circuit is an integrated circuit memory device comprising:

a storage array to store data received at the interface.

19. The integrated circuit of claim 18 wherein the first and second interfaces include a first and second transceiver, the first and second transceivers each coupled to a serializer and deserializer circuit.

20. The integrated circuit of claim 18 wherein the control circuit outputs the value in response to executable instructions.