Method and System for Fast Flow Control

• US 20080276029A1
• Filed: 05/03/2007
• Published: 11/06/2008
• Est. Priority Date: 05/03/2007
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Haraden, Ryan S.
• Application Number:
  US11/743,720
• Publication Number:
  US 20080276029A1
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]

Abstract

Flow of commands from logic under test, such as an FPGA, to a receiving component, such as a component in a PCIe hierarchy, is managed. A rate at which flow control signals are received by the logic under test from the receiving component is determined, the flow control signals indicating that there is space available in a buffer in the receiving component for receiving commands. The determined rate of receipt of the flow control signals is used for managing flow of commands from the logic under test to the receiving component without waiting for actual processing of flow control signals by the logic under test.

Claims

1. A method for managing flow of commands from logic under test to a receiving component, the method comprising:

determining a rate at which flow control signals are received by the logic under test from the receiving component over time, the flow control signals indicating that there is space available in a buffer in the receiving component to receive commands for performing transactions; and

using the determined rate of receipt of the flow control signals by the logic under test for managing flow of commands from the logic under test to the receiving component without waiting for actual processing of the flow control signals by the logic under test.

2. The method of claim 1, wherein the logic under test is a field programmable gate array (FPGA).

3. The method of claim 1, wherein the logic under test is connected to the receiving component via a Peripheral Component Interconnect Express (PCIe) link.

4. The method of claim 1, further comprising determining whether a flow control signal is actually received by the logic under test.

5. The method of claim 4, wherein if the flow control signal is not actually received by the logic, the method further comprises generating an error signal.

6. The method of claim 4, wherein if the flow control signal is not actually received by the logic, the method further comprises attempting recovery.

7. The method of claim 6, when attempting recovery comprises interrupting use of the determined rate of receipt of the flow control signals for controlling transmission of commands from the logic under test and waiting until actual processing of a flow control signal from the receiving component indicating buffer space is available in the receiving component for performing transactions before sending a command from the logic under test to the receiving component.

8. The method of claim 1, wherein the rate of receipt of flow control signals is determined based on a maximum delay recorded for receipt of a flow control signal within a window of acceptable delay.

9. The method of claim 4, wherein the step of determining whether a flow control signal is actually received by the logic under test includes determining whether the flow control signal is received within a window of acceptable delay.

10. The method of claim 9, wherein if the flow control signal is not received within a window of acceptable delay, the use of determined rate of receipt of the flow control signals for controlling transmission of commands from the logic under test is interrupted.

11. A system for managing flow of commands from logic under test to a receiving component, the system comprising:

logic under test; and

a receiving component receiving commands from the logic under test, wherein the receiving component transmits flow control signals to the logic under test indicating that there is space available in a buffer in the receiving component for receiving commands, and the logic under test manages flow of commands to the receiving component based on a determined rate of receipt of the flow control signals without waiting for actual processing of the flow control signals from the receiving component.

12. The system of claim 11, wherein the logic under test is a field programmable gate array (FPGA).

13. The system of claim 11, wherein the logic under test is connected to the endpoint via a Peripheral Component Interconnect Express (PCIe) link.

14. The system of claim 11, wherein the logic under test determines whether a flow control signal is actually received by the logic under test.

15. The system of claim 14, wherein if the flow control signal is not actually received by the logic under test, an error signal is generated.

16. The system of claim 14, wherein if the flow control signal is not actually received by the logic under test, recovery is attempted.

17. The system of claim 16, wherein recovery is attempted by interrupting use of the determined rate of receipt of the flow control signals for controlling transmission of commands from the logic under test and waiting until actual processing of a flow control signal from the receiving component before sending a command from the logic under test to the receiving component.

18. The system of claim 11, wherein the rate of receipt of flow control signals is determined based on a maximum delay recorded for receipt of a flow control signal within a window of acceptable delay.

19. The system of claim 14, wherein the logic under test determines whether the flow control signal is received within a window of acceptable delay.

20. The system of claim 19, wherein if the flow control signal is not received within a window of acceptable delay, the use of determined rate of receipt of the flow control signals for controlling transmission of commands from the logic under test is interrupted.