Memory with Block-Erasable Location

• US 20080276036A1
• Filed: 12/14/2006
• Published: 11/06/2008
• Est. Priority Date: 12/21/2005
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Van Acht, Victor M.G., Lambert, Niek
• Application Number:
  US12/158,838
• Publication Number:
  US 20080276036A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

A non-volatile main memory (10) comprises a plurality of physical blocks of memory locations. Pointing information (112a-c, 114a-c) is stored in the main memory (10), the pointing information comprising pointers (112a-c) to used blocks in use for particular functions and pointers (114a-c) to free blocks that are free for future use for the particular functions. The free blocks to replace selected ones of the used blocks. After this happens an updated version of the pointing information may be written to the main memory only after using at least two of the free blocks as replacements. On start up at least one of the pointers (114a-c) to the free blocks is used to access at least one of the free blocks and to determining whether the accessed free block has been used as a replacement for a particular one of the used blocks. If so, the free block is used instead of the particular one of the used blocks.

Claims

1. An apparatus comprising:

a non-volatile main memory that comprises a plurality of physical blocks of memory locations, the main memory supporting erasing of at least a physical block at a time;

a mapping control circuit configured to maintain pointing information stored in the main memory, the stored pointing information comprising pointers to use blocks that are in use for particular functions and pointers to free blocks that are free for future use for the particular functions, the mapping control circuit being configured to provide a substitute block, from the free blocks that the pointers point to, as substitute for at least part of a selected one of the used blocks, and to write an updated version of the pointing information to the main memory only after using at least two of the free blocks as substitute blocks at least after using one combination of at least two of the free blocks, the mapping control circuit being configured to use at least one of the pointers to free blocks from the stored pointer information, at least on start up, to access at least one of the free blocks to determine whether the at least one of the free blocks has been used as a substitute for a particular one of the used blocks and, if so, to use the at least one of the free blocks as substitute block for the particular one of the used blocks after start up.

2. An apparatus according to claim 1 wherein the main memory is a flash memory.

3. An apparatus according to claim 1, further comprising a working memory distinct from the main memory, in which apparatus the mapping control circuit is configured to store correction information in the working memory on start up, the correction information representing corrections to the pointing information, each correction indicating a respective one of the free blocks for which the mapping control circuit has determined that the free block is used as substitute block.

4. An apparatus according to claim 3, wherein the mapping control circuit is configured to cache changing parts of a mapping table that maps logical addresses to physical blocks, said correction information being kept stored in parallel with the changing parts.

5. An apparatus according to claim 3, wherein the mapping control circuit is configured to cache parts of the pointing information loaded from the main memory and to insert amendments in the loaded parts of the pointing information according to the stored correction information from the working memory.

6. An apparatus according to claim 3, wherein the mapping control circuit is configured to respond to a read command with a logical read block address by testing whether the logical read block address is covered by the stored correction information, to use the correction information to select a physical block when the logical read block address is covered and to use an address of a physical block that is defined in the used blocks for the logical read block address when the logical read block address is not covered.

7. An apparatus according to claim 1, wherein the pointing information comprises a mapping table, for mapping logical block addresses to physical block addresses, for respective segments of logical block addresses, mapping table segments for respective segments of logical block addresses being stored in respective different blocks, the mapping control circuit being configured to share use of the pointers to free blocks for selecting substitutes for the respective different blocks for storing different ones of the segments.

8. An apparatus according to claim 1, wherein the mapping control circuit is configured to receive a write command for a range of at least one address within a logical block, the mapping control circuit being configured to maintain a first and second physical block in the main memory for the logical block, the second block being selected from the free blocks pointed at by the pointing information, the first block containing a base version of the logical block, the mapping control circuit being configured to respond to the write command by writing only to a part of the addresses of the second physical block which comprises said range of at least one address, the mapping control circuit being configured to respond to a read command for the logical block by returning data from the second physical block or data from the first physical block, dependent on whether the read command addresses the logical block within said part.

9. An apparatus according to claim 8, wherein the mapping control circuit is configured to respond to the write command by copying data for addresses from a start of the first block to a start of said range, from the first block to the second writing and to write data for the range of addresses to the second blocky according to the write command, a remainder of the second block being left unwritten in response to the write command.

10. An apparatus according to claim 8, wherein the mapping control circuit is configured to use at least one of the pointers to one of the free blocks, selectively at least on start up, to access the second block, to determine whether the second block has been used to store data in said part and, if so, to use the second block to supply data from said second block in response to subsequent read commands that address said part.

11. An apparatus according to claim 10 further comprising a working memory, wherein the mapping control circuit is configured to store correction information in the working memory on start up, the correction information representing corrections to the pointing information, each correction indicating a respective one of the free blocks, for which it has been determined that the free block is used as said second block, and said part of the addresses in the second block.

12. An apparatus according to claim 8, wherein the mapping control circuit is configured to receive a further write command for a further range of addresses, to respond to said further write command by testing whether the further range overlaps with said part, to write data identified by the command in the second block in the case of no overlap and to write data identified by the command in a third block selected from the free blocks in the case of an overlap.

13. An apparatus according to claim 12, wherein the mapping control circuit is configured to copy remaining data from the first block to one of the second and third block, and to use said one of the second and third block instead of the first block subsequently, and to erase the first block after said copying.

14. An apparatus according to claim 1, wherein the mapping control circuit is configured to detect when all free blocks identified by the pointing information have been used, and to write an updated version of the pointing information to the main memory upon said detection, in which updated version original pointers to free blocks have been added to the pointers to the used blocks and original pointers to blocks that have been replaced by the free blocks have been removed from the pointers to the used blocks and added to the pointers to the free blocks.

15. An apparatus according to claim 14, wherein the mapping control circuit is configured to erase the blocks that have been replaced by the free blocks before writing the updated version of the pointing information to the main memory.

16. An apparatus according to claim 14, wherein the mapping control circuit is configured to write information identifying bad blocks of the main memory that have been permanently removed from further use into the main memory, the mapping control circuit being arranged to search said information identifying bad blocks at least on start up and to.

17. An apparatus according to claim 14, wherein the mapping control circuit is configured to receive a write command for a range of addresses within a logical block, the mapping control circuit being configured to maintain a first and second physical block for the logical block, the second block being selected from the free blocks pointed at by the pointing information, the first block containing a base version of the logical block, the mapping control circuit being configured to respond to the write command by writing only to a part of the addresses of the second physical block which comprises said range of addresses, the mapping control circuit being configured to respond to a read command for the logical block by returning data from the second physical block or data from the first physical block, dependent on whether the read command addresses the logical block within said part, the mapping control circuit being configured to respond to said detection that all free blocks identified by the pointing information have been used by copying remaining data from the first blocks to the second blocks and by including a pointer to the second block as a used block in the updated version of the pointing information.

18. A method of operating a non-volatile main memory that comprises a plurality of physical blocks of memory locations, the main memory supporting erasing of at least a physical block at a time, the method comprising:

store pointing information in the main memory, the pointing information comprising pointers to used blocks in use for particular functions and pointers to free blocks that are free for future use for the particular functions,

using the free blocks to replace selected ones of the used blocks;

writing an updated version of the pointing information to the main memory only after using at least two of the free blocks as replacements at least after using one combination of at least two of the free blocks,

using at least one of the pointers to the free blocks, selectively at least on start up, to access at least one of the free blocks

determining, selectively at least on start up, whether the accessed free block has been used as a replacement for a particular one of the used blocks and, if so,

using the free block instead of the particular one of the used blocks.