Semiconductor memory apparatus, memory access control system and data reading method

• US 20080276049A1
• Filed: 04/29/2008
• Published: 11/06/2008
• Est. Priority Date: 05/02/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Kajigaya, Kazuhiko
• Granted Patent: US 8,145,853 B2
• Time in Patent Office: Days
• US Class Current: 711/151
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and a priority operation control portion which chooses and outputs the data with a highest priority among the priority information and the data that are stored in the read data storing portion while maintaining a corresponding relationship between the priority information and the data.

Claims

1. A semiconductor memory apparatus, comprising:

a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address;

a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data;

a read data storing portion which stores both the data and the priority information while maintaining a corresponding relationship between the data and the priority information;

a data reading portion reads the data corresponding to the address information which is input by the read request input portion from the main memory;

a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and

a priority operation control portion which chooses and outputs the data with a highest priority among the priority information and the data that are stored in the read data storing portion while maintaining a corresponding relationship between the priority information and the data.

2. A semiconductor memory apparatus according to claim 1, further comprising a read data transport request input portion which receives a data transport request signal requesting to output the data, wherein

the priority operation control portion chooses the data with the highest priority when the read data transport request portion receives the read data transport request.

3. A semiconductor memory apparatus according to claim 1, wherein the read data storing portion comprises:

a plurality of registers which store both the data and the priority information while maintaining a corresponding relationship between the data and the priority information;

a read pointer portion which indicates a read address of the plurality of registers;

a write pointer portion which indicates a write address of the plurality of registers;

the read data registration portion stores the priority information and the data to the register pointed by the address indicated by the write pointer portion while maintaining a corresponding relationship between the priority information and the data, and

the priority operation portion chooses the register with a highest priority among the registers between the address pointed by the write pointer portion and the address pointed by the read pointer portion and reads the data stored in the chosen register.

4. A semiconductor memory apparatus according to claim 3, wherein

when the priority operation control portion chooses the register with the highest priority among the registers between the address pointed by the write pointer portion and the address pointed by the read pointer portion and reads the data stored in the chosen register, if the priority operation control portion detects a plurality of registers with the highest priority, the priority operation control portion chooses one of the multiple registers that is closest to the address pointed by the write pointer portion.

5. A semiconductor memory apparatus according to claim 3, wherein

each of the registers store a read flag which indicates whether or not the register has been read while maintaining a corresponding relationship between the flag and the priority information,

the read data registration portion sets the read flag of the register corresponding to the address pointed by the write pointer portion to “

unread”

when the read data registration portion stores the priority information and the data to the register pointed by the address indicated by the write pointer portion while maintaining a corresponding relationship between the priority information and the data, and

the priority operation control portion sets the read flag of the register with the highest priority to “

read”

when the priority operation control portion chooses the register with a highest priority and outputs the data stored in the chosen register.

6. A semiconductor memory apparatus according to claim 5, wherein

when the priority operation control portion chooses the register with the highest priority among the registers between the address pointed by the write pointer portion and the address pointed by the read pointer portion and reads the data stored in the chosen register, the priority operation control portion skips the register if the read flag of the register is “

read”

.

7. A semiconductor memory apparatus according to claim 1, wherein

the read request comprises storing area identification information which indicates a storing area at which the data which has been read is stored

corresponding relationships are maintained between the storing area identification information and the address information and between the storing area identification information and the priority information,

the data, the priority information and the storing area identification information are stored at the read data storing portion

the read data registration portion stores the priority information input by the read request input portion, the priority information, the storing area identification information and the data read by the data reading portion at the read data storing portion while maintaining a corresponding relationship thereof, and

the priority operation control portion chooses and outputs the priority information, the storing area identification information and the data while maintaining a corresponding relationship thereof that have the highest priority and have been stored at the read data storing portion while maintaining a corresponding relationship thereof.

8. A memory access control system which reads data from a semiconductor memory apparatus via a memory access control circuit, wherein

the memory access control circuit inputs a read request including:

address information which is referred to when the data is read from the semiconductor memory apparatus;

priority information which indicates priority of reading the data; and

storing area identification information which is used for determining a storing area of the read data while maintaining a corresponding relationship thereof, and comprises a read request transport portion which outputs the read request that has been input,

the semiconductor memory apparatus comprises;

a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address;

a read data storing portion which stores the data, priority, and storing area identification information while maintaining a corresponding relationship thereof;

a read request input portion receiving a read request from the memory access control circuit;

a data reading portion reads the data corresponding to address information included in the read request which is input by the read request input portion from the main memory;

a read data registration portion storing the priority information input by the read request input, the data read by the data reading portion and the storing area identification information to the read data storing portion while maintaining a corresponding relationship thereof; and

a priority operation control portion which chooses the data and the storing area identification information with a highest priority among the data, the priority and the storing area identification information stored in the read data storing portion and outputs the data and the storing area identification information to the memory access control portion while maintaining a corresponding relationship thereof, and

the memory access control circuit comprises a data storing portion which inputs the data and the storing area identification information from the semiconductor memory apparatus while maintaining a corresponding relationship thereof and stores the data based on the storing area identification information.

9. A memory access control system according to claim 8, wherein

the memory access control circuit comprises a read data transport request output portion which outputs a read data transport request signal which requests to output the data to the semiconductor memory apparatus,

the semiconductor memory apparatus comprises a read data transport request input portion which receives a data transport request signal from the memory access control circuit, and

the priority operation control portion outputs the data and the storing area identification information to the memory access control circuit when the read data transport request portion receives the read data transport request.

10. A memory access control system according to claim 8, wherein

the data storing portion inputs the data and the storing area identification information from the semiconductor memory apparatus and stores the data based on the storing area identification information in an order of inputting the data and the storing area identification information.

11. A memory access control system according to claim 8, wherein

the memory access control system comprises a storing area memory portion which stores the data while maintaining a corresponding relationship between the data and a storing area address,

the memory access control circuit comprises an address information storing portion for storing the priority and the storing address while maintaining a corresponding relationship thereof,

the read request transport portion stores the priority and the storing address at the address information storing portion while maintaining a corresponding relationship thereof, if the storing area identification information of the read request indicates the storing area memory portion and the storing area address is included in the storing area identification information,

if the data storing portion inputs the data and the storing area identification information from the semiconductor memory apparatus and the storing area identification information indicates the storing area memory portion, the data storing portion reads the storing area address with the highest priority from the address information storing portion and stores the data at the storing area memory portion of the storing area address.

12. A data reading method of a semiconductor memory apparatus which includes a main memory that stores data while maintaining a corresponding relationship between the data and an address, comprising:

a step of inputting a read request including both address information which is referred to when reading the data and priority information which indicates priority for reading the data while maintaining a corresponding relationship thereof;

a step of reading the data corresponding to the address information from the main memory;

a step of storing the read data and the priority information at a read data memory portion which stores the data and the priority information while maintaining a corresponding relationship thereof; and

a step of choosing and outputting the data with a highest priority among the data and the priority information stored in the read data memory portion.