Method and an Apparatus for Providing Timing Signals to a Number of Circuits, an Integrated Circuit and a Node

• US 20080276116A1
• Filed: 05/26/2006
• Published: 11/06/2008
• Est. Priority Date: 06/01/2005
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Teklatech A/S
• Inventors: Bjerregaard, Tobias
• Granted Patent: US 8,112,654 B2
• Time in Patent Office: Days
• US Class Current: 713/501
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical

Abstract

A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier.

Claims

1-52. -52. (canceled)

53. A method of providing timing signals to a number of circuits, the method comprising:

providing a plurality of interconnected nodes, each circuit being connected to a node, each node receiving a timing signal from one or more other nodes and transmitting a corresponding timing signal to at least one other node and/or a circuit(s) connected to the node,

providing a timing signal to one of the nodes,

at least one node receiving a timing signal from each of two or more nodes and not transmitting the corresponding timing signal to the at least one other node and/or a circuit(s) connected thereto, before a timing signal has been received from each of the two or more nodes,

positioning the nodes topologically in a number of dimensions defined by at least two non-parallel directions so that the node(s) adapted to receive a timing signal from a transmitting node are positioned further in at least one of the directions than the transmitting node, so that a timing skew is along the directions.

54. A method according to claim 53, wherein a plurality of the nodes receive a timing signal from two or more nodes and do not transmit the corresponding timing signal to the at least one other node, before a timing signal has been received from each of the two or more nodes.

55. A method according to claim 53, wherein one or more of the nodes, when receiving a first timing signal from one or more other nodes, transmit(s) an acknowledging signal to each of the one or more other node(s).

56. A method according to claim 55, wherein the one or more nodes further do not transmit a subsequent timing signal received from the other node(s), before having received an acknowledging signal from each of the node(s) to which a timing signal corresponding to the first timing signal has been transmitted.

57. A method according to claim 55, wherein the one or more nodes do not transmit the acknowledging signal(s) before having received timing signals from all nodes transmitting timing signals to the node.

58. A method according to claim 53, wherein at least one of the nodes receives a timing signal being a sequence, in time, of at least two different values, and transmits, to the other node(s), as the corresponding timing signal, the received timing signal inversed so that higher and lower values are interchanged in the same timing sequence.

59. A method according to claim 53, the method further comprising the step of two of the circuits interchanging data, the interchanging of data being controlled by the timing signals received by the circuits from each of two of the nodes.

60. A method according to claim 58, the method of interchanging data comprising each circuit transmitting or receiving data in connection with a change, in the timing signal received, from a lower of the two or more values to a higher of the values or a change from the higher to the lower of the values.

61. A method according to claim 60, wherein the two circuits are adapted to transmit or receive data in connection with the same change and are connected to two neighbouring nodes or two nodes between which an even number of the at least one node(s) exist.

62. A method according to claim 53, wherein the positioning step comprises positioning the nodes physically over the predetermined area.

63. A method according to claim 53, wherein the nodes are provided at least substantially in positions corresponding to an intersection of one line of a plurality of at least substantially equidistantly positioned lines along a first direction and one line of a plurality of at least substantially equidistantly positioned lines along a second direction being non-parallel to the first direction.

64. A method of preparing an integrated circuit, the method comprising,providing a number of circuits,providing a clock generating or receiving node,providing a number of relay nodes, each circuit being connected to a node, each relay node being adapted to receive a signal from one or more nodes and transmit a signal to at least one other relay node and/or a circuit connected thereto,interconnecting the nodes so that a signal from the receiving/generating node will cause a signal transmitted to all relay nodes and all circuits,

wherein:

step

     3) comprises providing at least one of the relay nodes as a node adapted to receive a signal from at least two relay nodes and to not forward a signal to any other relay nodes and/or a circuit connected thereto, until a signal has been received from each of the at least two relay nodes,

step

     3) comprises positioning the nodes topologically in a number of dimensions, defined by two non-parallel directions, so that the node(s) adapted to receive a timing signal from a transmitting node are positioned further in at least one of the directions than the transmitting node and so that a timing skew is along the directions, and

step

     4) comprises interconnecting the at least one relay node so as to receive signals from the at least two relay nodes.

65. A method according to claim 64, wherein step 3) comprises providing a plurality of the nodes adapted to receive a timing signal from two or more nodes and to not transmit the corresponding timing signal to the at least one other node, before a timing signal has been received from each of the two or more nodes.

66. A method according to claim 64, wherein step 3) comprises providing one or more of the nodes adapted to, when receiving a first timing signal from one or more other nodes, transmit(s) an acknowledging signal to each of the one or more other node(s).

67. A method according to claim 66, wherein the one or more nodes are further adapted to not transmit a subsequent timing signal received from the other node(s), before having received an acknowledging signal from each of the node(s) to which a timing signal corresponding to the first timing signal has been transmitted.

68. A method according to claim 66, wherein step 3) comprises providing the one or more nodes adapted to not transmit the acknowledging signal(s) before having received timing signals from all nodes transmitting timing signals to the node.

69. A method according to claim 64, wherein step 3) comprises providing at least one of the nodes receiving a timing signal being a sequence, in time, of at least two different values, and transmits, to the other node(s), as the corresponding timing signal, the received timing signal inversed so that high and low values are interchanged in the same timing sequence.

70. A method according to claim 64, the method further comprising providing two of the circuits with means for interchanging data, the interchanging means controllable by the timing signals received by the circuits from each of two of the nodes.

71. A method according to claim 69, the interchanging means each being adapted to transmit or receive data in connection with a change, in the timing signal received, from a lower of the two or more values to a higher of the values or a change from the higher to the lower of the values.

72. A method according to claim 71, wherein the two circuits are adapted to transmit or receive data in connection with the same change and are connected to two neighbouring nodes or two nodes between which an even number of the at least one node(s) exist.

73. A method according to claim 64, wherein the positioning step of step 3) comprises positioning the nodes physically in the dimensions, so that the node(s) adapted to receive a timing signal from a transmitting node are positioned further in at least one of the directions than the transmitting node.

74. A method according to claim 64, wherein step 1) comprises providing the circuits on the surface, so that at least a predetermined distance exists between neighbouring circuits, and wherein step 4) comprises interconnecting the nodes with electrical connections primarily positioned between the circuits.

75. A method according to claim 64, wherein step 3) comprises positioning the nodes at least substantially in positions corresponding to an intersection of one line of a plurality of at least substantially equidistantly positioned lines along a first direction and one line of a plurality of at least substantially equidistantly positioned lines along a second direction being non-parallel to the first direction.

76. An apparatus for providing timing signals to a number of circuits, the apparatus comprising:

a plurality of interconnected nodes, each circuit being connected to a node, each node being adapted to receive a timing signal from one or more other nodes and to transmit a corresponding timing signal to at least one other node and/or a circuit(s) connected to the node, the nodes being topologically positioned in a number of dimensions defined by at least two non-parallel directions, the node(s) adapted to receive a timing signal from a transmitting node being positioned further in at least one of the directions than the transmitting node so that a timing skew is along the directions,

a circuit for providing a timing signal to one of the nodes,

at least one node being adapted to receive a timing signal from each of two or more nodes and to not transmit the corresponding timing signal to the at least one other node and/or a circuit(s) connected thereto, before a timing signal has been received from each of the two or more nodes.

77. An apparatus according to claim 76, wherein each of a plurality of the nodes is adapted to receive a timing signal from two or more nodes and to not transmit the corresponding timing signal to the at least one other node and/or a circuit, before a timing signal has been received from each of the two or more nodes.

78. An apparatus according to claim 76, wherein one or more of the nodes are adapted to, when receiving a first timing signal from one or more other nodes, transmit an acknowledging signal to each of the one or more other node(s).

79. An apparatus according to claim 78, wherein the one or more nodes are further adapted to not transmit a subsequent timing signal received from the other node(s), before having received an acknowledging signal from each of the node(s) to which a timing signal corresponding to the first timing signal has been transmitted.

80. An apparatus according to claim 78, wherein the one or more nodes are adapted to not transmit the acknowledging signal(s) before having received timing signals from all nodes transmitting timing signals to the node.

81. An apparatus according to claim 76, wherein at least one of the nodes is adapted to receive a timing signal being a sequence, in time, of at least two different values, and to transmit, to the other node(s), as the corresponding timing signal, the received timing signal inversed so that higher and lower values are interchanged in the same timing sequence.

82. An apparatus according to claim 76, wherein two of the circuits comprise means for interchanging data, the interchanging means being controllable by the timing signals received by the circuits from each of two of the nodes.

83. An apparatus according to claim 81, wherein the interchanging means are adapted to each transmit or receive data in connection with a change, in the timing signal received, from a lower of the at least two values to a higher of the values or a change from the higher to the lower of the values.

84. An apparatus according to claim 83, wherein the two circuits are adapted to transmit or receive data in connection with the same change and are connected to two neighbouring nodes or two nodes between which an even number of the at least one node(s) exist.

85. An apparatus according to claim 76, wherein the nodes are physically positioned over a predetermined area defined by at least two non-parallel directions, the node(s) adapted to receive a timing signal from a transmitting node being positioned further in at least one of the directions than the transmitting node.

86. An apparatus according to claim 76, wherein the nodes are provided at least substantially in positions corresponding to an intersection of one line of a plurality of at least substantially equidistantly positioned lines along a first direction and one line of a plurality of at least substantially equidistantly positioned lines along a second direction being non-parallel to the first direction.

87. An integrated circuit comprising,a number of circuits,a clock generating or receiving node,a number of relay nodes, each circuit being connected to a node, each relay node being adapted to receive a signal from one or more nodes and transmit a signal to at least one other relay node and/or a circuit connected thereto, the nodes being topologically positioned in a number of dimensions, defined by two non-parallel directions, so that the node(s) adapted to receive a timing signal from a transmitting node are positioned further in at least one of the directions than the transmitting node so that a timing skew is along the directions, andinterconnecting elements interconnecting the nodes so that a signal from the receiving/generating node causes a signal transmitted to all relay nodes and all circuits,

wherein at least one of the relay nodes is interconnected with at least two relay nodes and adapted to not forward a signal to any other relay nodes and/or a circuit connected thereto, until a signal has been received from each of the at least two relay nodes.

88. A circuit according to claim 87, wherein step 3) comprises providing a plurality of the nodes adapted to receive a timing signal from two or more nodes and to not transmit the corresponding timing signal to the at least one other node, before a timing signal has been received from each of the two or more nodes.

89. A circuit according to claim 87, wherein step 3) comprises providing one or more of the nodes to be adapted to, when receiving a first timing signal from one or more other nodes, transmit an acknowledging signal to each of the one or more other node(s).

90. A circuit according to claim 89, wherein the one or more nodes are further adapted to not transmit a subsequent timing signal received from the other node(s), before having received an acknowledging signal from each of the node(s) to which a timing signal corresponding to the first timing signal has been transmitted.

91. A circuit according to claim 89, wherein the one or more nodes are adapted to not transmit the acknowledging signal(s) before having received timing signals from all nodes transmitting timing signals to the node.

92. A circuit according to claim 87, wherein at least one of the nodes is adapted to receive a timing signal being a sequence, in time, of at least two different values, and to transmit, to the other node(s), as the corresponding timing signal, the received timing signal inversed so that higher and lower values are interchanged in the same timing sequence.

93. A circuit according to claim 87, wherein two of the circuits comprise means for interchanging data, the interchanging means being controllable by the timing signals received by the circuits from each of two of the nodes.

94. A circuit according to claim 92, wherein the interchanging means each are adapted to transmit or receive data in connection with a change, in the timing signal received, from a lower of the at least two values to a higher of the values or a change from the higher to the lower of the values.

95. A circuit according to claim 94, wherein the two circuits are adapted to transmit or receive data in connection with the same change and are connected to two neighbouring nodes or two nodes between which an even number of the at least one node(s) exist.

96. A circuit according to claim 87, wherein the nodes are physically positioned over the predetermined area, so that the node(s) adapted to receive a timing signal from a transmitting node are positioned further in at least one of the directions than the transmitting node.

97. A circuit according to claim 87, wherein the circuits are positioned on the surface, so that at least a predetermined distance exists between neighbouring circuits, and wherein the interconnecting means are primarily positioned between the circuits.

98. A circuit according to claim 87, wherein the nodes are positioned at least substantially in positions corresponding to an intersection of one line of a plurality of at least substantially equidistantly positioned lines along a first direction and one line of a plurality of at least substantially equidistantly positioned lines along a second direction being non-parallel to the first direction.