METHOD FOR PERFORMING FAILURE MODE AND EFFECTS ANALYSIS OF AN INTEGRATED CIRCUIT AND COMPUTER PROGRAM PRODUCT THEREFOR

• US 20080276206A1
• Filed: 04/11/2008
• Published: 11/06/2008
• Est. Priority Date: 04/13/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: YOGITECH S.p.A (Intel Corporation)
• Inventors: MARIANI, Riccardo
• Granted Patent: US 7,937,679 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G01R 31/2846 using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
• CPC Class Codes: G06F 11/2252 using fault dictionaries
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 2117/02 Fault tolerance, e.g. for transient fault suppression
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method for performing failure mode and effects analysis (FMEA) on integrated circuits including preparing a FMEA database of an integrated circuit under design and computing FMEA results from the FMEA database. Information is automatically extracted from an integrated circuit description. The extraction of information includes reading integrated circuit information, partitioning the circuit in invariant and elementary sensitive zones (SZ), using the information in the preparation step of a FMEA database. Optionally a FMEA validation stage may be performed with which FMEA computed results are compared with FMEA measured results to obtain FMEA validated results.

Claims

1. A method for performing failure mode and effects analysis (FMEA) on integrated circuits comprising:

preparing a FMEA database of a integrated circuit under design and computing FMEA results from said FMEA database,

automatically extracting information from a integrated circuit description, said extraction of information comprising;

reading integrated circuit information,

partitioning said circuit in invariant and elementary sensitive zones (SZ), and

using said information in the preparing the FMEA database.

2. The method of claim 1, wherein said partitioning said circuit in invariant and elementary sensitive zones (SZ) includes, considering a plurality of abstraction levels defining said circuit description and taking as invariant sensitive zones, the zones appearing from a top level to a bottom level among said abstraction levels.

3. The method of claim 1 wherein said partitioning said circuit in invariant and elementary sensitive zones (SZ) includes taking as a elementary sensitive zone the smallest meaningful partition of the integrated circuit at the abstraction level in which one of the functions performed by such circuit or part of them can be identified.

4. The method of claim 1 further comprising extracting the circuit usage profile from a circuit workload and of using said profile in said preparation step of a FMEA database.

5. The method of claim 1 further comprising entering information related to the circuit safety specifications and based on safety norms guidelines in said preparation step of a FMEA database.

6. The method of claim 1 further comprising a step of validation of the FMEA database using the circuit workload and a subsequent step of extraction of measured FMEA results from said measured FMEA database or a repetition of said preparation step of a FMEA database.

7. The method of claim 1 further comprising extracting input cone (IL) information and of extracting output cone (OL) information in order to compose a sensitive zones database.

8. The method of claim 7, further comprising generating a fault-list (LF) by parsing said input (IL) and output (OL) logic cones and generating a fault-list database.

9. The method of claim 7, further comprising extracting information on shared elements by evaluating the correlation between each sensitive zone (SZ) in terms of shared elements, gates and nets, and creating a sharing database.

10. The method of claim 1 wherein said step of preparing a FMEA database of a electronic circuit under design includes a step of importing said sensitive zones database in said FMEA database.

11. The method of claim 10, wherein said FMEA database includes presenting records, each of the records corresponding to a possible failure mode (FM) of a given sensitive zone (SZ) and each record includes a sensitive zone field, a failure mode field, a FMEA statistics field and a diagnostic coverage field.

12. The method of claim 10 wherein said FMEA database automatically computes fault model statistics for each FMEA record.

13. The method of claim 11, further comprising presenting one or more field of said records for receiving for each sensitive zone (SZ) a failure mode (FM) representing the effect of faults (G) in the sensitive zone (SZ) leading to an error, on the basis of the circuit description, the safety specifications and the safety norm guidelines.

14. The method of claim 11, further comprising presenting said failure mode field of said records for receiving in the each sensitive zone (SZ) an expected main effect (ME) representing a certain failure mode (FM) of the corresponding sensitive zone (SZ) with respect to an observation point (OP).

15. The method of claim 14, further comprising presenting said FMEA statistics field of said records for receiving for each sensitive zone (SZ) expected usage frequency values.

16. The method of claim 15, further comprising presenting said FMEA statistics field of said records for receiving for each sensitive zone (SZ) safe and dangerous values.

17. The method of claim 16, wherein said receiving for each sensitive zone (SZ) safe and dangerous values includes receiving an estimated Safe fraction and Dangerous fraction of the possible failures for the given failure mode (FM) in the given sensitive zone (SZ), divided in transient and permanent faults.

18. The method of claim 16, wherein said FMEA database automatically computes failure rates for each FMEA record and on the basis of said computed failure rates computes FMEA results without diagnostic.

19. The method of claim 18, further comprising receiving for each sensitive zone (SZ) the diagnostic coverage.

20. The method of claim 19, wherein said receiving for each sensitive zone (SZ) the diagnostic coverage includes performing an auto-coverage computation, taking in account for DDF estimations (DDF AUTO (TR), DDF AUTO (PE)) the logic sharing between the sensitive zones (SZ) on the basis of said sharing database.

21. The method of claim 19, wherein said receiving for each sensitive zone (SZ) the diagnostic coverage includes performing an auto-coverage computation includes using for each sensitive zone (Z) a shape function to weight the sharing degree with other sensitive zones.

22. The method of claim 11, wherein FMEA database automatically computes detected/undetected failure rates for each FMEA record and on the basis of said computed detected/undetected failure rates computes FMEA results with diagnostic.

23. The method of claim 12, wherein said fault models are built distinguishing faults (G) originating failures (F) occurring in a sensitive zone (SZ) between permanent and transient/intermittent faults.

24. The method of claim 23, further comprising distinguishing said permanent faults in “

permanent ON”

, “

permanent OFF” and

“

permanent ST”

depending on when they are occurring in system operation mode.

25. The method of claim 6 wherein the step of validation of the FMEA database includes a workload acceptance phase, that includes a functional coverage measurement of said circuit workload and a fault coverage measurement that makes use of the fault list database.

26. The method of claim 25, further comprising testing the results of the functional coverage measurement and of the fault coverage measurement.

27. The method of claim 26, wherein the testing yields a positive result, includes performing a fault injection operation for local faults and a fault injection operation for global faults in the sensitive zones (SZ) indicated in the sensitive zone database.

28. The method of claim 26, further comprising performing a fault coverage analysis taking all diagnostic outputs as observation points (OP) for the fault coverage measurement.

29. The method of claim 28, wherein said fault coverage analysis includes three sequential runs, a first run taking as observation points (OP) all the primary input/outputs of said integrated circuit under design coming from the circuit description and the circuit workload, a second run taking all the diagnostic outputs of said microelectronic circuits as observation points (OP), a third run measuring the diagnostic coverage due to SW diagnostic test for each sensitive zone (SZ).

30. The method of claim 28, further comprising a post-processing for elaborating the results of fault injection and fault coverage steps and a collection of the FMEA validation results.

31. The method of claim 30, wherein said post-processing and said collection includes a post processing flow for the norm IEC 61508 suitable for collecting indices required by said IEC 61508 norm.

32. The method of claim 31, wherein said post processing flow for the norm IEC 61508 is performed in three sequential specific runs, the runs comprising:

a first specific run for calculating as index the product of Dangerous Failure to Failure value (D*F) for each sensitive zone (SZ) taken from the sensitive zone database by a specific postprocessing;

a second specific run for calculating as index a total dangerous detected failure rate for permanent ON faults (DFF_ON) value for each sensitive zone (SZ) taken from the sensitive zone database by said specific postprocessing;

a third specific run for calculating as index a total dangerous detected failure rate for both permanent OFF and permanent ST faults (DDF_OFFST) value for each sensitive zone (SZ) taken from the database (214) by said postprocessing; and

wherein said specific postprocessing comprising parsing fault simulation reports and fault list database, dividing faults for the different sensitive zones (SZ) defined in the sensitive zone database, computing initial index values, applying a manipulation of said index values.

33. The method of claim 32, further comprising comparing between computed FMEA results and measured FMEA results and if a result of the comparing is below an acceptable threshold said repetition of said preparation step of a FMEA database is performed, if the result of said comparison yields a positive results, validated FMEA results are produced.

34. A processing apparatus configured for performing the steps of the method of claim 1.

35. A computer program product directly loadable in the memory of a computer and comprising software code portions for performing the method of claim 1 when the product is run on a computer.