Mask Pattern Designing Method Using Optical Proximity Correction in Optical Lithography, Designing Device, and Semiconductor Device Manufacturing Method Using the Same

• US 20080276215A1
• Filed: 03/28/2006
• Published: 11/06/2008
• Est. Priority Date: 03/28/2005
• Status: Abandoned Application

• Current Assignee: National Institute of Advanced Industrial Science and Technology (Government of Japan), Runesas Technology Corporation
• Original Assignee: National Institute of Advanced Industrial Science and Technology (Government of Japan), Runesas Technology Corporation
• Inventors: Tanaka, Toshihiko, Higuchi, Tetsuya, Murakawa, Masahiro, Terasawa, Tsuneo, Yoshioka, Nobuyuki, Sakanashi, Hidenori, Nosato, Hirokazu
• Application Number:
  US11/910,049
• Publication Number:
  US 20080276215A1
• Time in Patent Office: Days
• US Class Current: 716/20
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06N 3/126 Evolutionary algorithms, e.g. genetic algorithms or genetic programming
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A method for designing a mask pattern realizes shortening the ever-growing time for the OPC treatment, decreases the fabrication TAT of a semiconductor device and cuts cost. A method for fabricating a semiconductor device uses the mask pattern designed. This invention performs the OPC treatment in advance on a cell library constituting the basic configuration of a semiconductor circuit pattern and prepares a semiconductor chip using the cell library that has undergone the OPC treatment. The method for designing a mask pattern includes the steps of designing a cell library pattern by executing for each of the cell libraries a treatment for correcting proximity effect directed to correcting the change of shape taking place during the formation of a pattern by the exposure of a mask pattern, designing a mask pattern by laying out the cell libraries and changing the amount of correction of proximity effect applied to the cell libraries in consideration of the influence of the cell library patterns disposed peripherally. This treatment for correction is executed by the degree of influence exerted by surrounding patterns collected in advance and the genetic algorithm.

Claims

1. A method for designing a mask pattern, comprising the steps of acquiring cell libraries having undergone a treatment of optical proximity correction directed to correcting a change of shape taking place during formation of a pattern by exposure of a mask pattern to light, laying out the cell libraries to design a mask pattern and changing an amount of the optical proximity correction given to cells in consideration of an influence of surrounding cell patterns.

2. A method for designing a mask pattern according to claim 1, wherein the step of designing the mask pattern comprises a step of defining and registering a variable to be adjusted for the purpose of implementing the optical proximity correction.

3. A method for designing a mask pattern according to claim 2, further comprising the steps of comprehending a degree of influence of surrounding patterns and optimizing the variable, thereby correcting the cell libraries.

4. A method for designing a mask pattern according to claim 3, wherein the step of optimizing the variable is effected by the genetic algorithm method.

5. A computer program consisting of an algorithm possessing a function of executing the method for designing a mask pattern according to any one of claims 1 to 4.

6. A semiconductor device fabricated using the mask pattern formed by the method for designing a mask pattern according to any one of claims 1 to 4.

7. A method for manufacturing an electronic circuit device, comprising the step of using the mask pattern formed by the method for designing a mask pattern according to any one of claims 1 to 4.

8. A method for designing a mask pattern set forth in any one of claims 1 to 4, further comprising the step for changing a peripheral region of a single cell having undergone the process of optical proximity correction in consideration of an influence of peripherally disposed cell library patterns.

9. A method for fabricating a semiconductor device, comprising the step of using a mask pattern whose gate pattern has been corrected by the method for designing a mask pattern according to any one of claims 1 to 4.

10. A method for fabricating a semiconductor device according to claim 9, wherein the gate pattern has an adjusting variable that is a gate width and/or a gate length.

11. A method for fabricating a semiconductor device, comprising the step of using a mask pattern whose isolation-forming pattern has been corrected by the method for designing a mask pattern according to any one of claims 1 to 4.

12. A method for fabricating a semiconductor device according to claim 11, wherein the isolation-forming pattern has an adjusting variable that is a width of a diffusion layer region, an amount of retraction, an amount of projection or a combination thereof.

13. A method for manufacturing a semiconductor device, comprising the step of using a mask pattern whose contact pattern has been corrected by the method for designing a mask pattern according to any one of claims 1 to 4.

14. A method for fabricating a semiconductor device according to claim 13, wherein the contact pattern has an adjusting variable that is a height, a width and a central position.

15. A method for fabricating a semiconductor device, comprising the steps of using a mask pattern formed by the method for designing a mask pattern according to any one of claims 1 to 4 and using a single-wafer processing.