SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20080277661A1
• Filed: 05/01/2008
• Published: 11/13/2008
• Est. Priority Date: 05/11/2007
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kobayashi, Takashi, MACHIDA, Shuntaro
• Granted Patent: US 8,106,395 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: B81C 99/0045 End test of the packaged device
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/05554 being square

Abstract

A technique of manufacturing a semiconductor device capable of performing a probe test by a common test apparatus as normal LSI chips even for large-area chips is provided. A chip comprising a device formed on a device area by a semiconductor process and including a plurality of test areas sectioned by chip areas is prepared. Next, pads to be electrically connected to the device are formed at corresponding positions on the respective plurality of test areas. Subsequently, the respective test areas are tested by a same probe card via the plurality of pads.

Claims

1. A semiconductor device comprising a chip having a plurality of first pads and a plurality of second pads which are electrically connected to a device formed on a main surface of a substrate,

wherein the plurality of first pads and the plurality of second pads are layouted at corresponding positions in a plurality of areas having a same size made by sectioning the main surface of the chip.

2. The semiconductor device according to claim 1,

wherein the chip further has a third pad electrically connected to the first pad,

wherein the third pad is layouted outside the plurality of areas,

wherein the first pad is not wire-bonded, and

wherein the second pad and the third pad are wire-bonded.

3. The semiconductor device according to claim 1,

wherein the chip further has a plurality of fourth pads not electrically connected to the device, and

wherein the plurality of fourth pads are layouted at corresponding positions in the respective plurality of areas.

4. The semiconductor device according to claim 1,

wherein the plurality of first pads and the plurality of second pads are layouted so that the layout is same in the respective plurality of areas as the chip is moved in parallel.

5. The semiconductor device according to claim 1,

wherein the plurality of first pads and the plurality of second pads are layouted so that the layout is same in the respective plurality of areas as the chip is rotated by 90°

and moved or rotated by 180°

.

6. The semiconductor device according to claim 1,

wherein the chip has a rectangular shape and a length of one side is equal to or larger than 3 cm.

7. The semiconductor device according to claim 1,

wherein the device comprises:

a first electrode provided on the substrate;

a hollow portion provided on the first electrode; and

a second electrode provided on the hollow portion,

wherein the first pad is electrically connected to the first electrode, and

wherein the second pad is electrically connected to the second electrode.

8. A method of manufacturing a semiconductor device comprising the steps of:

(a) preparing a substrate having a plurality of first areas and a plurality of second areas sectioned by the respective plurality of first areas and comprising a device formed by a semiconductor process in the first area;

(b) forming a plurality of first pads and a plurality of second pads electrically connected to the device at corresponding positions in the respective plurality of second areas after the step (a);

(c) respectively testing the plurality of second areas by a same probe card via the plurality of first pads and the plurality of second pads after the step (b); and

(d) dicing the substrate and taking out a plurality of chips from the plurality of first areas after the step (c).

9. The method of manufacturing a semiconductor device according to claim 8,

wherein the plurality of first pads and the plurality of second pads are layouted so that the layout is same in the respective plurality of second areas as the chip is moved in parallel in the step (b).

10. The method of manufacturing a semiconductor device according to claim 8,

wherein the plurality of first pads and the plurality of second pads are layouted so that the layout is same in the respective plurality of second areas as the chip is rotated by 90°

and moved or rotated by 180°

in the step (b).

11. The method of manufacturing a semiconductor device according to claim 8 further comprising the steps of:

(e) layouting a third pad electrically connected to the plurality of first pads outside the plurality of second areas at the same time with the step (b); and

(f) performing wire bonding to the second pad and the third pad after the step (d).

12. The method of manufacturing a semiconductor device according to claim 11 further comprising the step of:

(g) cutting the electrical connection between the first pad and the third pad near the third pad after the step (c) and before the step (f).

13. The method of manufacturing a semiconductor device according to claim 8,

wherein a plurality of fourth pads are formed at corresponding positions in the respective plurality of second areas,

wherein the fourth pad in at least one area of the plurality of second areas is electrically connected to the device, and

wherein the fourth pads on the other areas of the plurality of second areas are not electrically connected to the device.