SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING UPPER PATTERN ALIGNED WITH LOWER PATTERN MOLDED BY SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING THE SAME

• US 20080277795A1
• Filed: 07/18/2008
• Published: 11/13/2008
• Est. Priority Date: 02/21/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: SHIN, Soo-Ho, HONG, Hyeong-Sun, RYU, Ho-In, KIM, Bong-Soo
• Granted Patent: US 7,595,529 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

Provided are semiconductor integrated circuit (IC) devices having an upper pattern aligned with a lower pattern molded by a semiconductor substrate and methods of forming the same. In the semiconductor IC devices, the lower pattern contacts the upper pattern using an active region and/or an isolation layer. The methods include preparing a semiconductor substrate having an active region. A lower pattern is formed on the active region. The lower pattern is surrounded by the active region and protrudes from a top surface of the active region. An upper pattern is disposed on the lower pattern. The upper pattern contacts the lower pattern.

Claims

1. A semiconductor integrated circuit device comprising:

a semiconductor substrate having an active region;

an upper pattern disposed in a predetermined region of the semiconductor substrate, the upper pattern protruding upward from a top surface of the active region and extending downward from the top surface of the active region; and

a lower pattern including a buried plug and a buried capping pattern disposed on the buried plug, the buried plug disposed below the top surface of the active region and contacting the upper pattern through the predetermined region of the semiconductor substrate, and the buried capping pattern protruding from the top surface of the active region and surrounding the upper pattern,

wherein the upper pattern has different widths on the buried plug.

2. The device according to claim 1, wherein the upper pattern includes a bit line pattern and is formed of at least one conductive material.

3. The device according to claim 2, further comprising:

an interconnection insulating layer interposed between the active region and the upper pattern and interposed between the active region and the lower pattern; and

impurity diffusion regions disposed in the active region and disposed adjacent to the lower pattern to overlap the buried plug,

wherein the buried plug is formed of a conductive material,

wherein the buried capping pattern is formed of an insulating material,

wherein a portion of the interconnection insulating layer between the active region and the upper pattern is formed of a different material than a portion of the interconnection insulating layer between the active region and the lower pattern, and

wherein the lower pattern is a gate pattern.

4. The device according to claim 2, further comprising:

an interconnection insulating layer interposed between the active region and the upper pattern and between the active region and the lower pattern; and

impurity diffusion regions disposed in the active region and disposed adjacent to the lower pattern to overlap the buried plug,

wherein the buried plug is formed of a conductive material,

wherein the buried capping pattern is formed of an insulating material,

wherein a portion of the interconnection insulating layer between the active region and the upper pattern is formed of the same material as a portion of the interconnection insulating layer between the active region and the lower pattern, and

wherein the lower pattern is a gate pattern.

5. A semiconductor integrated circuit device comprising:

a semiconductor substrate having an isolation layer;

an upper pattern disposed in a predetermined region of the semiconductor substrate, the upper pattern protruding upward from a top surface of the isolation layer and extending downward from the top surface of the isolation layer; and

a lower pattern including a buried plug and a buried capping pattern disposed on the buried plug, the buried plug disposed below the top surface of the isolation layer to be surrounded by the upper pattern through the predetermined region of the semiconductor substrate to contact the upper pattern, and the buried capping pattern protruding from the top surface of the isolation layer and surrounding the upper pattern,

wherein the upper pattern has the same width on the buried plug.

6. The device according to claim 5, wherein the upper pattern includes a bit line pattern and is formed of at least one conductive material.

7. The device according to claim 6, wherein

the buried plug is formed of a conductive material,

the buried capping pattern is formed of an insulating material, and

the lower pattern is a gate pattern.

8. A semiconductor integrated circuit device comprising:

a semiconductor substrate having an active region and an isolation layer surrounding the active region;

first and second upper patterns disposed in predetermined regions of the semiconductor substrate, the first upper pattern protruding upward from a top surface of the active region and extending downward from the top surface of the active region, the second upper pattern protruding upward from a top surface of the isolation layer and extending downward from the top surface of the isolation layer;

a first lower pattern including a first buried plug and a first buried capping pattern disposed on the first buried plug, the first buried plug disposed below the top surface of the active region and contacting the first upper pattern through one of the predetermined regions of the semiconductor substrate, and the first buried capping pattern protruding from the top surface of the active region and surrounding the first upper pattern; and

a second lower pattern including a second buried plug and a second buried capping pattern disposed on the second buried plug, the second buried plug disposed below the top surface of the isolation layer to be surrounded by the second upper pattern through another one of the predetermined regions of the semiconductor substrate to contact the second upper pattern, and the second buried capping pattern protruding from the top surface of the isolation layer and surrounding the second upper pattern,

wherein the first upper pattern has different widths on the first buried plug, and

wherein the second upper pattern has the same width on the second buried plug.

9. The device according to claim 8, wherein each of the first and second upper patterns includes a bit line pattern and is formed of at least one conductive material.

10. The device according to claim 9, further comprising:

an interconnection insulating layer interposed between the active region and the first upper pattern and between the active region and the first lower pattern; and

impurity diffusion regions disposed in the active region and disposed adjacent to the first lower pattern to overlap the first buried plug,

wherein the first buried plug is formed of a conductive material,

wherein the first buried capping pattern is formed of an insulating material,

wherein a portion of the interconnection insulating layer between the active region and the first upper pattern is formed of a different material than a portion of the interconnection insulating layer between the active region and the first lower pattern, and

wherein the first lower pattern is a gate pattern.

11. The device according to claim 9, further comprising:

an interconnection insulating layer interposed between the active region and the first upper pattern and between the active region and the first lower pattern; and

impurity diffusion regions disposed in the active region and disposed adjacent to the first lower pattern to overlap the first buried plug,

wherein the first buried plug is formed of a conductive material,

wherein the first buried capping pattern is formed of an insulating material,

wherein a portion of the interconnection insulating layer between the active region and the first upper pattern is formed of the same material as a portion of the interconnection insulating layer between the active region and the first lower pattern, and

wherein the first lower pattern is a gate pattern.

12. The device according to claim 9, wherein

the second buried plug is formed of a conductive material,

the second buried capping pattern is formed of an insulating material, and

the second lower pattern is a gate pattern.

13. A method of forming a semiconductor integrated circuit device, comprising:

preparing a semiconductor substrate having an active region;

forming a trench in the active region;

forming a lower pattern in the trench, the lower pattern having a buried plug and a buried capping pattern stacked sequentially, the buried capping pattern protruding from a top surface of the active region defining the trench;

forming an interlayer insulating layer on the active region to cover the lower pattern;

forming a connection hole in the interlayer insulating layer, the connection hole exposing the buried plug and a portion of the active region adjacent to the buried plug; and

forming an upper pattern filling the connection hole.

14. The method according to claim 13, wherein the forming of the upper pattern comprises:

forming an electrode layer on the interlayer insulating layer to fill the connection hole;

forming a photoresist pattern on the electrode layer;

etching the electrode layer using the photoresist pattern as an etch mask until the interlayer insulating layer is exposed; and

removing the photoresist pattern from the semiconductor substrate.

15. The method according to claim 14, wherein the electrode layer is formed of at least one conductive material and the upper pattern is a bit line pattern.

16. The method according to claim 15, wherein the forming of the connection hole comprises:

forming a photoresist layer on the interlayer insulating layer, the photoresist layer having an opening exposing a portion of the interlayer insulating layer and overlapping the buried plug;

sequentially etching the interlayer insulating layer and the buried capping pattern using the photoresist layer as an etch mask and using the active region and the buried plug as an etch buffer layer; and

removing the photoresist layer from the semiconductor substrate.

17. The method according to claim 13, wherein the forming of the trench comprises:

forming a material layer on the active region;

forming a photoresist layer on the material layer, the photoresist layer having an opening exposing a portion of the material layer;

sequentially etching the material layer and the semiconductor substrate using the photoresist layer as an etch mask; and

removing the photoresist layer from the semiconductor substrate.

18. The method according to claim 17, wherein the forming of the lower pattern comprises:

forming a buried layer on the material layer to fill the trench;

etching back the buried layer using the material layer as an etch buffer layer to form the buried plug, the buried plug partially filling the trench;

forming a buried capping layer on the material layer to cover the buried plug and to fill the trench;

partially etching the buried capping layer and the material layer to form the buried capping pattern on the buried plug; and

removing the material layer from the semiconductor substrate.

19. The method according to claim 13, further comprising:

forming an interconnection insulating layer between the active region and the upper pattern and between the active region and the lower pattern; and

forming impurity diffusion regions in the active region to be adjacent to the lower pattern and overlap the buried plug,

wherein the buried plug is formed of a conductive material,

wherein the buried capping pattern is formed of an insulating material,

wherein the lower pattern is a gate pattern, and

wherein a portion of the interconnection insulating layer between the active region and the upper pattern is formed of a different material than a portion of the interconnection insulating layer between the active region and the lower pattern.

20. The method according to claim 13, further comprising:

forming an interconnection insulating layer between the active region and the upper pattern and between the active region and the lower pattern; and

forming impurity diffusion regions in the active region to be adjacent to the lower pattern and overlap the buried plug,

wherein the buried plug is formed of a conductive material,

wherein the buried capping pattern is formed of an insulating material,

wherein the lower pattern is a gate pattern, and

wherein a portion of the interconnection insulating layer between the active region and the upper pattern is formed of the same material as a portion of the interconnection insulating layer between the active region and the lower pattern.

21. A method of forming a semiconductor integrated circuit device, comprising:

preparing a semiconductor substrate having an isolation layer;

forming a trench in the isolation layer;

forming a lower pattern in the trench, the lower pattern having a buried plug and a buried capping pattern stacked sequentially, the buried capping pattern protruding from a top surface of the isolation layer defining the trench;

forming an interlayer insulating layer on the isolation layer to cover the lower pattern;

forming a connection hole in the interlayer insulating layer, the connection hole exposing the buried plug and a portion of the isolation layer adjacent to the buried plug and under the buried plug; and

forming an upper pattern filling the connection hole.

22. The method according to claim 21, wherein the forming of the upper pattern comprises:

forming an electrode layer on the interlayer insulating layer to fill the connection hole;

forming a photoresist pattern on the electrode layer;

etching the electrode layer using the photoresist pattern as an etch mask until the interlayer insulating layer is exposed; and

removing the photoresist pattern from the semiconductor substrate.

23. The method according to claim 22, wherein the electrode layer is formed of at least one conductive material and the upper pattern is a bit line pattern.

24. The method according to claim 23, wherein the forming of the connection hole comprises:

forming a photoresist layer on the interlayer insulating layer, the photoresist layer having an opening exposing a portion of the interlayer insulating layer and overlapping the buried plug;

etching the interlayer insulating layer, the isolation layer and the buried capping pattern using the photoresist layer as an etch mask and using the buried plug as an etch buffer layer; and

removing the photoresist layer from the semiconductor substrate.

25. The method according to claim 21, wherein the forming of the trench comprises:

forming a material layer on the isolation layer;

forming a photoresist layer on the material layer, the photoresist layer having an opening exposing a portion of the material layer;

sequentially etching the material layer and the isolation layer using the photoresist layer as an etch mask; and

removing the photoresist layer from the semiconductor substrate,

wherein the material layer is formed of at least one material.

26. The method according to claim 25, wherein the forming of the lower pattern comprises:

forming a buried layer on the material layer to fill the trench;

etching back the buried layer using the material layer as an etch buffer layer to form the buried plug, the buried plug partially filling the trench;

forming a buried capping layer on the material layer to cover the buried plug and to fill the trench;

partially etching the buried capping layer and the material layer to form the buried capping pattern on the buried plug; and

removing the material layer from the semiconductor substrate.

27. The method according to claim 21, wherein

the buried plug is formed of a conductive material,

the buried capping pattern is formed of an insulating material, and

the lower pattern is a gate pattern.

28. A method of forming a semiconductor integrated circuit device, comprising:

preparing a semiconductor substrate having an active region and an isolation layer surrounding the active region;

forming first and second trenches in the active region and the isolation layer, respectively;

forming first and second lower patterns in the first and second trenches, respectively, the first lower pattern having a first buried plug and a first buried capping pattern stacked sequentially, the second lower pattern having a second buried plug and a second buried capping pattern stacked sequentially, the first and second buried capping patterns protruding from top surfaces of the active region and the isolation layer, respectively;

forming an interlayer insulating layer on the active region and the isolation layer to cover the first and second lower patterns;

forming first and second connection holes in the interlayer insulating layer, the first connection hole exposing the first buried plug and a portion of the active region adjacent to the first buried plug, the second connection hole exposing the second buried plug and a portion of the isolation layer adjacent to the second buried plug and under the second buried plug; and

forming first and second upper patterns filling the first and second connection holes, respectively.

29. The method according to claim 28, wherein the forming of the first and second upper patterns comprises:

forming an electrode layer on the interlayer insulating layer to fill the first and second connection holes;

forming photoresist patterns on the electrode layer;

etching the electrode layer using the photoresist patterns as an etch mask until the interlayer insulating layer is exposed; and

removing the photoresist patterns from the semiconductor substrate.

30. The method according to claim 29, wherein the electrode layer is formed of at least one conductive material and each of the first and second upper patterns is a bit line pattern.

31. The method according to claim 30, wherein the forming of the first and second connection holes comprises:

forming a photoresist layer on the interlayer insulating layer, the photoresist layer having openings exposing portions of the interlayer insulating layer and overlapping respective ones of the first and second buried plugs;

etching the interlayer insulating layer, the isolation layer, and the first and second buried capping patterns using the photoresist layer as an etch mask and using the first and second buried plugs and the active region as an etch buffer layer; and

removing the photoresist layer from the semiconductor substrate.

32. The method according to claim 28, wherein the forming of the first and second trenches comprises:

forming a material layer on the active region and the isolation layer;

forming a photoresist layer on the material layer, the photoresist layer having openings exposing portions of the material layer and disposed on respective ones of the active region and the isolation layer;

etching the material layer, the active region, and the isolation layer using the photoresist layer as an etch mask; and

removing the photoresist layer from the semiconductor substrate,

wherein the material layer is formed of at least one material.

33. The method according to claim 32, wherein the forming of the first and second lower patterns comprises:

forming a buried layer on the material layer to fill the first and second trenches;

etching back the buried layer using the material layer as an etch buffer layer to form the first and second buried plugs, the first and second buried plugs partially filling the first and second trenches, respectively;

forming a buried capping layer on the material layer to cover the first and second buried plugs and to fill the first and second trenches;

partially etching the buried capping layer and the material layer to form the first and second buried capping patterns on respective ones of the first and second buried plugs; and

removing the material layer from the semiconductor substrate.

34. The method according to claim 28, wherein

the first and second buried plugs are formed of a conductive material, and

the first and second buried capping patterns are formed of an insulating material.

35. The method according to claim 28, further comprising:

forming an interconnection insulating layer between the active region and the first upper pattern and between the active region and the first lower pattern; and

forming impurity diffusion regions in the active region to be adjacent to the first lower pattern and overlap the first buried plug,

wherein each of the first and second lower patterns is a gate pattern, and

wherein a portion of the interconnection insulating layer between the active region and the first upper pattern is formed of a different material than a portion of the interconnection insulating layer between the active region and the first lower pattern.

36. The method according to claim 28, further comprising:

forming an interconnection insulating layer between the active region and the first upper pattern and between the active region and the first lower pattern; and

forming impurity diffusion regions in the active region to be adjacent to the first lower pattern and overlap the first buried plug,

wherein each of the first and second lower patterns is a gate pattern, and

wherein a portion of the interconnection insulating layer between the active region and the first upper pattern is formed of the same material as a portion of the interconnection insulating layer between the active region and the first lower pattern.