IRREGULAR VOLTAGE DETECTION AND CUTOFF CIRCUIT USING BANDGAP REFERENCE VOLTAGE GENERATION CIRCUIT

• US 20080278133A1
• Filed: 04/16/2008
• Published: 11/13/2008
• Est. Priority Date: 05/10/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang-hoon
• Granted Patent: US 7,960,960 B2
• Time in Patent Office: Days
• US Class Current: 323/284
• CPC Class Codes: H02H 3/207 also responsive to under-voltage window comparators for indication G01R19/165

Abstract

An irregular voltage detection and cutoff circuit using a bandgap reference voltage generation circuit includes the bandgap reference voltage generation circuit, which generates a bandgap reference voltage from the power-supply voltage, a reference voltage generator, which generates a first reference voltage and a second reference voltage in the same voltage level as the bandgap reference voltage from the power-supply voltage, a voltage detector, which generates a detection voltage from the power-supply voltage, and a comparator, which generates a switching control signal that cuts off the power-supply voltage by comparing the first and second reference voltages with the detection voltage.

Claims

1. An irregular voltage detection and cutoff circuit, which monitors an operating voltage range of a power-supply voltage, the irregular voltage detection and cutoff circuit comprising:

a bandgap reference voltage generation circuit, which generates a bandgap reference voltage from the power-supply voltage;

a reference voltage generator, which generates a first reference voltage and a second reference voltage at a same voltage level as the bandgap reference voltage from the power-supply voltage;

a voltage detector, which generates a detection voltage from the power supply voltage; and

a comparator, which generates a switching control signal that cuts off the power-supply voltage by comparing the first and second reference voltages with the detection voltage.

2. The irregular voltage detection and cutoff circuit of claim 1, wherein the reference voltage generator comprises:

an OP amp, wherein the bandgap reference voltage is inputted to a non-inverting input terminal thereof and the first reference voltage is inputted to an inverting input terminal thereof;

a PMOS transistor, whose gate is connected to an output of the OP amp, whose source is connected to the power-supply voltage, and whose drain is connected to the first reference voltage;

a first resistor, which is connected between the first reference voltage and the second reference voltage; and

a second resistor, which is connected between the second reference voltage and a ground voltage.

3. The irregular voltage detection and cutoff circuit of claim 2, wherein the voltage detector comprises:

a third resistor, which is connected between the power-supply voltage and the detection voltage; and

a fourth resistor, which is connected between the detection voltage and the ground voltage.

4. The irregular voltage detection and cutoff circuit of claim 3, wherein the third and fourth resistors have a resistance ratio of

5. The irregular voltage detection and cutoff circuit of claim 3, wherein the first through fourth resistors have a resistance ratio of

6. The irregular voltage detection and cutoff circuit of claim 1, wherein the comparator comprises:

a first comparator, which compares the first reference voltage and the detection voltage;

a second comparator, which compares the second reference voltage and the detection voltage; and

a logic circuit, which generates the switching control signal by AND operating an output of the first comparator and an output of the second comparator.

7. The irregular voltage detection and cutoff circuit of claim 1, wherein the bandgap reference voltage generation circuit comprises:

an OP amp, which provides an output of the OP amp as a bias voltage and compares a first voltage and a second voltage;

a first NMOS transistor, which is connected between the output of the OP amp and a ground voltage and whose gate is connected to a reset signal;

a first PMOS transistor, which is connected between the power-supply voltage and the first voltage and whose gate is connected to the output of the OP amp;

a second PMOS transistor, which is connected between the power-supply voltage and the second voltage and whose gate is connected to the output of the OP amp;

a third PMOS transistor, which is connected between the power-supply voltage and the bandgap reference voltage and whose gate is connected to the output of the OP amp;

a first resistor, which is connected between the first voltage and the ground voltage;

a first diode, which is connected between the first voltage and the ground voltage;

a second resistor, which is connected between the second voltage and the ground voltage;

a third resistor and a second diode group, which are connected in series between the second voltage and the ground voltage; and

a fourth resistor, which is connected between the bandgap reference voltage and the ground voltage.

8. The irregular voltage detection and cutoff circuit of claim 7, wherein the OP amp comprises:

a fourth PMOS transistor, whose source is connected to the power-supply voltage and whose gate is connected to the output of the OP amp;

fifth and sixth PMOS transistors, whose sources are connected to a drain of the fourth PMOS transistor and whose gates are respectively connected to the first voltage and second voltage;

second and third NMOS transistors, which are respectively connected between drains of the fifth and sixth PMOS transistors and the ground voltage and whose drains and gates are connected to each other;

a fourth NMOS transistor, whose gate is connected to the gate of the second NMOS transistor and whose source is connected to the ground voltage so as to form a current mirror with the second NMOS transistor;

a fifth NMOS transistor, whose drain is connected to the output of the OP amp, whose gate is connected to the gate of the third NMOS transistor, and whose source is connected to the ground voltage so as to form a current mirror with the third NMOS transistor;

a seventh PMOS transistor, whose source is connected to the power-supply voltage, and whose drain and gate are connected to a drain of the fourth NMOS transistor; and

an eighth PMOS transistor, whose source is connected to the power-supply voltage, whose drain is connected to the output of the OP amp, and whose gate is connected to a gate of the seventh PMOS transistor so as to form a current mirror with the seventh PMOS transistor.

9. The irregular voltage detection and cutoff circuit of claim 7, wherein the second diode group is formed of a plurality of diodes connected in parallel between the third resistor and the ground voltage.

10. The irregular voltage detection and cutoff circuit of claim 1, wherein the switching control signal turns on or off a switch connecting the power-supply voltage and a main system.