PROGRAMMABLE LOGIC DEVICE WITH EMBEDDED SWITCH FABRIC

• US 20080278197A1
• Filed: 07/22/2008
• Published: 11/13/2008
• Est. Priority Date: 07/12/2002
• Status: Active Grant

• Current Assignee: SCA Technica, Inc.
• Original Assignee: SCA Technica, Inc.
• Inventors: Murotake, David K.
• Granted Patent: US 7,733,125 B2
• Time in Patent Office: Days
• US Class Current: 326/38
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/0028 wherein the AD/DA conversion occurs at baseband stage
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes

Abstract

The invention in the simplest form is a programmable logic device consisting of gate arrays, external I/O endpoints, and an embedded switch fabric configurable for connecting gates to gates, endpoints to endpoints and gates to endpoints. The architecture may employ a fabric interface of non-blocking crossbar switches for making complex bus connections of multiple devices to facilitate high speed processing.

Claims

1. A programmable logic device, comprising:

at least one gate array;

external I/O endpoints; and

an embedded switched fabric.

2. The programmable logic device of claim 1, where the embedded switched fabric comprises a crossbar switch.

3. The programmable logic device of claim 1, where the embedded switched fabric is configurable.

4. The programmable logic device of claim 1, where the embedded switched fabric is connectible to external devices.

5. The programmable logic device of claim 1, where the embedded switched fabric is connectible to an embedded processor.

6. The programmable logic device of claim 1, where the embedded switched fabric is connectible to an embedded memory.

7. The programmable logic device of claim 1, where the embedded switched fabric is connectible to an I/O device.

8. The programmable logic device of claim 1, where the embedded switched fabric is connectible to file storage.

9. The programmable logic device of claim 1, where the embedded switched fabric is connectible to a multimedia device.

10. The programmable logic device of claim 1, comprising a field programmable gate array (FPGA).

11. The programmable logic device of claim 1, comprising a complex programmable logic device (CPLD).

12. The programmable logic device of claim 1, comprising a system on chip (SOC) device.

13. The programmable logic device of claim 1, comprising a cell computing device.

14. The programmable logic device of claim 1, where the embedded switched fabric is connectible to the gate array.

15. The programmable logic device of claim 14, said gate array comprising multiple connectible endpoints.

16. The programmable logic device of claim 15, comprising implemented processing whereby a said gate is connected to a said connectible endpoint for inter-chip and external communication.

17. The programmable logic device of claim 1, where one said external I/O endpoint is a serial transceiver.

18. The programmable logic device of claim 1, where one said external I/O endpoint is a Ethernet MAC Block.

19. A programmable logic device, comprising:

at least one reconfigurable gate array;

external I/O endpoints; and

a configurable, embedded switched fabric with multiple endpoints connectible in multiple locations within the reconfigurable gate array and endpoints connectible to external I/O endpoints.

20. The programmable logic device of claim 19, where the embedded switched fabric is a multi port crossbar connectible to embedded processors.