PACKAGED ANTENNA AND METHOD FOR PRODUCING SAME

• US 20080278400A1
• Filed: 05/09/2007
• Published: 11/13/2008
• Est. Priority Date: 05/09/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lachner, Rudolf, Lohninger, Gerhard, Forstner, Johann P.
• Granted Patent: US 9,103,902 B2
• Time in Patent Office: Days
• US Class Current: 343/873
• CPC Class Codes: G01S 7/03 Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01Q 1/38 formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 1/40 Radiating elements coated with or embedded in protective material
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H01Q 9/285 Planar dipole H01Q9/065 takes precedence; patch antenna H01Q9/0407
• CPC Class Codes: Y10T 29/49016 Antenna or wave energy "plumbing" making

Abstract

Electronic apparatus having an antenna chip with a substrate and an antenna structure, and a method of producing the same. The antenna chip is integrated or packaged in a package having a clip mounting surface for mounting the antenna chip, and an encapsulating material. The encapsulating material typically is a plastic mold used in the industrial packaging of integrated circuits. Between the antenna structure and the chip mounting surface, a first void is disposed in the substrate.

Claims

1. An electronic apparatus, comprising:

an antenna chip comprising a substrate and an antenna structure;

a package comprising a chip mounting surface and an encapsulating material; and

a first void arranged in the substrate in the vicinity of the antenna structure.

2. The apparatus of claim 1, wherein the first void is produced by etching.

3. The apparatus of claim 1, wherein the substrate is a silicon substrate.

4. The apparatus of claim 1, wherein a vertical projection of the first void onto the antenna structure has substantially the same largest diameter as the largest diameter of the antenna structure or a larger diameter than the largest diameter of the antenna structure.

5. The apparatus of claim 1, further comprising a second void is arranged between the antenna structure and the encapsulating material.

6. The apparatus of claim 1, further comprising a high frequency circuit.

7. The apparatus of claim 6, further comprising an additional high frequency circuit chip.

8. The apparatus of claim 7, wherein the high frequency circuit chip and the antenna chip are connected via interconnects selected from the group of interconnects consisting of wirebonds and bumps.

9. The apparatus of claim 7, wherein the high frequency circuit chip is based on SiGe-technology.

10. The apparatus of claim 1, wherein the high frequency circuit chip and the antenna chip are both mounted on the substrate.

11. The apparatus of claim 1, further comprising a filter chip.

12. The apparatus of claim 11, wherein the filter circuit chip and the antenna chip are connected via interconnects selected from the group of interconnects consisting of wirebonds and bumps.

13. The apparatus of any of claim 1, wherein the apparatus is a radar sensor following at least one principle selected from the group of principles consisting of continuous wave, continuous wave/Doppler, Frequency Modulated Continuous Wave (FMCW), and pulsed mode.

14. The apparatus of claim 1, wherein the package comprises interconnects selected from the group of interconnects consisting of balls and lands to connect the package to a printed circuit board.

15. The apparatus of claim 1, wherein the antenna has a size smaller than 2 mm².

16. The apparatus of claim 1, wherein the encapsulating material is a mold compound or a lid.

17. The apparatus of claim 16, wherein the encapsulating material is a lid comprising an opening.

18. The apparatus of claim 1, wherein the chip mounting surface comprises conducting areas and non-conducting areas.

19. The apparatus of claim 1, wherein the chip mounting surface comprises an opening adjacent to the void in the antenna substrate.

20. The apparatus of claim 1, further comprising a membrane separating the antenna structure from the first void arranged in the substrate.

21. The apparatus of claim 1, wherein the void is segmented.

22. An electronic apparatus, comprising:

an antenna chip comprising a substrate and an antenna structure;

a package comprising a chip mounting surface and an encapsulating material;

a cap covering the antenna structure; and

a second void disposed between the antenna structure and the cap.

23. The apparatus of claim 22, wherein the substrate is a silicon substrate.

24. The apparatus of claim 22, wherein a vertical projection of the second void onto the antenna structure has substantially the same largest diameter as the largest diameter of the antenna structure or a larger diameter than the largest diameter of the antenna structure.

25. The apparatus of claim 22, further comprising a first void arranged in the substrate between the antenna structure and the chip mounting surface.

26. The apparatus of claim 25, wherein the first void is produced by etching.

27. The apparatus of claim 22, further comprising a high frequency circuit.

28. The apparatus of claim 27, further comprising a high frequency circuit chip.

29. The apparatus of claim 28, wherein the high frequency circuit chip and the antenna chip are connected via interconnects chosen from the group of interconnects consisting of wirebonds and bumps.

30. The apparatus of claim 28, wherein the high frequency circuit chip and the antenna chip are both mounted on the substrate.

31. The apparatus of claim 28, wherein the high frequency circuit chip is based on SiGe-technology.

32. The apparatus of claim 22, further comprising a filter chip.

33. The apparatus of claim 32, wherein the filter circuit chip and the antenna chip are connected via interconnects chosen from the group consisting of wirebonds and bumps.

34. The apparatus of claim 22, wherein the antenna has a size smaller than 2 mm².

35. The apparatus of claim 22, wherein the apparatus works as a radar sensor following at least one principle selected from the group of principles consisting of continuous wave, continuous wave/Doppler, Frequency Modulated Continuous Wave (FMCW), and pulsed mode.

36. The apparatus of claim 22, wherein the package comprises interconnects selected from the group of interconnects consisting of balls and lands to connect the package to a printed circuit board.

37. The apparatus of claim 22, wherein the chip mounting surface comprises conducting areas and non-conducting areas.

38. The apparatus of claim 22, wherein the chip mounting surface comprises an opening adjacent to the antenna structure.

39. The apparatus of claim 22, wherein the cap comprises a conducting inner surface.

40. A method of producing an electronic apparatus comprising an antenna chip and a package, comprising:

a) providing a substrate;

b) producing an antenna structure on an upper face of the substrate;

c) producing a first void in the substrate;

d) disposing the substrate on a chip mounting surface of the package; and

f) providing an encapsulating material as a package to seal the antenna chip.

41. The method of claim 40, wherein the first void in the substrate is produced by etching the substrate.

42. The method of claim 41, wherein the substrate is etched until the void extends through the substrate to the antenna structure.

43. The method of claim 41, wherein the substrate is etched until the void extends through the substrate to a membrane supporting the antenna structure.

44. The method of claim 40, further comprising after step c):

c2) disposing a cap on the upper face of the substrate, wherein the size and shape of the cap is chosen to completely cover the antenna structure.

45. The method of claim 40, further comprising before step e):

d2) connecting the antenna chip to the contacts of the package.

46. The method of claim 45, wherein step d2) is carried out using flip-chip technology.

47. The method of claim 45, wherein step d2) is carried out by applying wire-bonding.

48. The method of claim 40, wherein the package is a Thin Small Leadless Package (TSLP).

49. The method of claim 40, wherein the antenna structure comprises aluminum.

50. A method of producing an electronic apparatus comprising an antenna chip and a package, comprising:

a) providing a substrate;

b) producing an antenna structure on an upper face of the substrate;

c) disposing a cap on the upper face of the substrate covering the antenna structure;

d) disposing the substrate on a chip mounting surface of the package; and

e) providing an encapsulating material to seal the antenna chip.

51. The method of claim 50, further comprising before step e):

d2) connecting the antenna chip to the contacts of the package.

52. The method of claim 51, wherein step d2) is carried out using flip-chip technology.

53. The method of claim 51, wherein step d2) is carried out by applying wire-bonding.

54. The method of claim 50, wherein the package is a Thin Small Leadless Package (TSLP).