Display and electronic apparatus

• US 20080278410A1
• Filed: 04/23/2008
• Published: 11/13/2008
• Est. Priority Date: 05/11/2007
• Status: Abandoned Application

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Uchino, Katsuhide, Yamashita, Junichi
• Application Number:
  US12/081,927
• Publication Number:
  US 20080278410A1
• Time in Patent Office: Days
• US Class Current: 345/55
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 71/621 Providing a shape to conductive layers, e.g. patterning or selective deposition
• CPC Class Codes: H10K 71/861 Repairing

Abstract

A display is disclosed, having an interconnect layout that allows easy repairing of a short-circuit defect even at the intersection of row and column interconnects. The display includes: row interconnects configured to be disposed along rows; column interconnects configured to be disposed along columns; and pixels configured to be disposed corresponding to intersections of the row and column interconnects arranged in a lattice manner. Each of the pixels includes at least a sampling transistor, a drive transistor, a holding capacitor, and a light-emitting element. The sampling transistor is turned on in response to a control signal supplied from one of the interconnects to thereby sample a video signal supplied from another of the interconnects and write the video signal to the holding capacitor. The drive transistor supplies the light-emitting element with a drive current dependent upon the video signal written to the holding capacitor.

Claims

1. A display comprising:

row interconnects configured to be disposed along rows;

column interconnects configured to be disposed along columns; and

pixels configured to be disposed corresponding to intersections of the row and column interconnects arranged in a lattice manner;

each of the pixels including at least a sampling transistor, a drive transistor, a holding capacitor, and a light-emitting element,

the sampling transistor turning on in response to a control signal supplied from one of the interconnects to thereby sampling a video signal supplied from another of the interconnects and writing the video signal to the holding capacitor,

the drive transistor supplying the light-emitting element with a drive current dependent upon the video signal written to the holding capacitor, wherein

the row interconnects and the column interconnects are formed of the same conductive layer, and at an intersection of the row and column interconnects, one interconnect is cut away,

the other interconnect crosses the one interconnect in such a manner as to pass through an absent part arising from the cutting-away of the one interconnect,

a pair of ends of the one interconnect, facing each other across the absent part, are connected to each other by a different interconnect,

the different interconnect is formed of a different conductive layer isolated from the row and column interconnects by an interlayer insulating film, and the different interconnect intersects with the other interconnect in such a manner as to avoid the absent part, to thereby permit repairing of a short-circuit defect between the end of the one interconnect and the other interconnect, caused at the absent part.

2. The display according to claim 1, wherein

the short-circuit defect is attributed to etching residue between the end of the one interconnect and the other interconnect, resulting from formation of the interconnects by etching, and

the different interconnect avoids the absent part in such a way the short-circuit defect attributed to the etching residue is permitted to be removed by laser light irradiation.

3. The display according to claim 1, wherein

the short-circuit defect is attributed to foreign matter attached to the absent part, and

the different interconnect avoids the absent part in such a way the short-circuit defect attributed to the foreign matter attached to the absent part is permitted to be removed by laser light irradiation.

4. The display according to claim 1, wherein

the row interconnects include interconnects for supplying a control signal to the pixels and interconnects for supplying a supply voltage to the pixels,

the column interconnects include interconnects for supplying a video signal to the pixels, and

at least the interconnects for supplying a supply voltage and the interconnects for supplying a video signal are formed of the same conductive layer.

5. The display according to claim 1, wherein each of the pixels has a threshold voltage correction function for cancelling the influence of the threshold voltage of the drive transistor.

6. The display according to claim 1, wherein each of the pixels has a mobility correction function for cancelling the influence of the mobility of the drive transistor.

7. An electronic apparatus comprising the display according to claim 1.