Devices, Systems, and Methods Regarding Camera Imaging

• US 20080278598A1
• Filed: 05/08/2008
• Published: 11/13/2008
• Est. Priority Date: 05/11/2007
• Status: Abandoned Application

• Current Assignee: Microscan Systems Inc (Omron Corporation)
• Original Assignee: Microscan Systems Inc (Omron Corporation)
• Inventors: Greenberg, Michael Philip, Murphy, Thomas G.
• Application Number:
  US12/117,011
• Publication Number:
  US 20080278598A1
• Time in Patent Office: Days
• US Class Current: 348/222.1
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: H04N 1/0058 using at least one dead-end path, e.g. using a sheet ejection path
• CPC Class Codes: H04N 1/00981 by forced convection, e.g. using fans
• CPC Class Codes: H04N 1/00989 by natural convection, e.g. using fins without a fan
• CPC Class Codes: H04N 1/2112 using still video cameras
• CPC Class Codes: H04N 1/32358 using picture signal storage, e.g. at transmitter H04N1/17 takes precedence
• CPC Class Codes: H04N 2201/0084 Digital still camera

Abstract

Certain exemplary embodiments can provide a method that can comprise automatically rendering an image. The image can be transferred to a memory from a digital camera via a Field Programmable Gate Array (FPGA) device. The FPGA device can be adapted to transfer image information from the digital camera to a memory.

Claims

1. A method comprising:

automatically rendering an image, said image transferred to a memory from a digital camera via a Field Programmable Gate Array (FPGA) device, said FPGA device adapted to transfer image information from said digital camera to a main memory of a processor via a first direct memory access (DMA) channel, said FPGA device adapted to receive a set of image pixels from said processor via a second DMA channel, said set of image pixels corresponding to a rectangular region of said image, said FPGA device adapted to process said set of image pixels, said FPGA device adapted to transfer said set of image pixels to said processor via said second DMA channel.

2. The method of claim 1, further comprising:

processing said set of image pixels at said FPGA device.

3. The method of claim 1, further comprising:

performing a binary morphology on said set of image pixels at said FPGA device.

4. The method of claim 1, further comprising:

transferring said image information to said processor via a pixel buffer of said FPGA device.

5. The method of claim 1, further comprising:

transferring said set of image pixels to said processor via a results buffer of said FPGA device.

6. The method of claim 1, further comprising:

reading said set of image pixels from a results buffer of said FPGA device via a Peripheral Connect Interface (PCI) target register read operation.

7. The method of claim 1, further comprising:

performing a Sobel Filter operation on said set of image pixels at said FPGA device.

8. The method of claim 1, wherein:

said set of image pixels is a portion of a grayscale image determined from said image and said FPGA device is adapted to process said portion of said grayscale image and output a City block Sobel image.

9. The method of claim 1, wherein:

said set of image pixels is a portion of a grayscale image determined from said image and said FPGA device is adapted to process said portion of said grayscale image and output a binarized grayscale image.

10. The method of claim 1, wherein:

said set of image pixels is a portion of a grayscale image determined from said image and said FPGA device is adapted to process said portion of said grayscale image and output a binarized Sobel image.

11. The method of claim 1, wherein:

said set of image pixels is a portion of a grayscale image determined from said image and said FPGA device is adapted to process said portion of said grayscale image and output a sum of Sobel values for pixels of said set of image pixels with a grayscale value that exceeds a predetermined threshold.

12. The method of claim 1, wherein:

said set of image pixels is a portion of a grayscale image determined from said image and said FPGA device is adapted to process said portion of said grayscale image and output a count of Sobel values for pixels of said set of image pixels with a grayscale value that exceeds a predetermined threshold.

13. The method of claim 1, wherein:

said set of image pixels is a binarized image and said FPGA device is adapted to modify said binarized image based upon a specified border value and a height of said rectangular region of said image.

14. The method of claim 1, wherein:

said set of image pixels is a binarized image and said FPGA device is adapted to perform break detection via colored pixels of said binarized image.

15. The method of claim 1, wherein:

said set of image pixels is a grayscale image and said FPGA device is adapted to process said grayscale image and output image data that comprises a central pixel replaced by a minimum neighborhood value.

16. The method of claim 1, wherein:

said set of image pixels is a grayscale image and said FPGA device is adapted to process said grayscale image and output image data that comprises a central pixel replaced by a maximum neighborhood value.

17. A machine-readable medium comprising machine instructions for activities comprising:

automatically rendering an image, said image transferred to a memory from a digital camera via a Field Programmable Gate Array (FPGA) device, said FPGA device adapted to transfer image information from said digital camera to a main memory of a processor via a first direct memory access (DMA) channel, said FPGA device adapted to receive a set of image pixels from said processor via a second DMA channel, said set of image pixels corresponding to a rectangular region of said image, said FPGA device adapted to process said set of image pixels, said FPGA device adapted to transfer said set of image pixels to said processor via said second DMA channel.

18. A system comprising:

a digital camera adapted to obtain an image;

a processor; and

a Field Programmable Gate Array (FPGA) device, said FPGA device adapted to transfer image information from said digital camera to a main memory of a processor via a first direct memory access (DMA) channel, said FPGA device adapted to receive a set of image pixels from said processor via a second DMA channel, said set of image pixels corresponding to a rectangular region of said image information, said FPGA device adapted to process said set of image pixels, said FPGA device adapted to transfer said set of image pixels to said processor via said second DMA channel.