Method of forming a fine pattern of a semiconductor device using a resist reflow measurement key
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Abstract
In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.
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Citations
35 Claims
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1-15. -15. (canceled)
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16. A method of forming a fine pattern of a semiconductor device, the method comprising:
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forming a resist pattern on a semiconductor substrate to form a pattern having a predetermined shape; forming a resist reflow measurement key on the semiconductor substrate while forming the resist pattern; reflowing the resist pattern and the resist reflow measurement key at the same time; measuring a variation in a position of a first center point of the reflowed resist reflow measurement key and a variation in a position of a second center point of the reflowed resist reflow measurement key; and determining a critical dimension of the reflowed resist pattern from measurement values of the variation in the position of the first center point and the variation in the position of the second center point. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method of controlling a reflow process on a pattern of a semiconductor device, the method comprising:
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forming a resist pattern on a semiconductor substrate to form the pattern having a predetermined shape; forming a resist reflow measurement key on the semiconductor substrate while forming the resist pattern; reflowing the resist pattern and the resist reflow measurement key at the same time; measuring a variation in a position of a first center point of the reflowed resist reflow measurement key and a variation in a position of a second center point of the reflowed resist reflow measurement key; determining a critical dimension of the reflowed resist pattern from measurement values of the variation in the position of the first center point and the variation in the position of the second center point; and altering conditions of reflowing in accordance with a determined critical dimension. - View Dependent Claims (32, 33, 34, 35)
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Specification