Receiver circuit and amplifier circuit

• US 20080280578A1
• Filed: 05/06/2008
• Published: 11/13/2008
• Est. Priority Date: 05/08/2007
• Status: Abandoned Application

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Nimura, Yoshihiko
• Application Number:
  US12/149,669
• Publication Number:
  US 20080280578A1
• Time in Patent Office: Days
• US Class Current: 455/249.1
• CPC Class Codes: H03F 1/342 in field-effect transistor amplifiers
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 3/3063 using at least one transistor as controlling device, the transistor being used as a variable impedance device
• CPC Class Codes: H03H 11/245 using field-effect transistor

Abstract

A receiver circuit includes an attenuator that receives a received signal and attenuates the received signal, a DC level shifter that shifts a DC level of an attenuated signal from the attenuator, an amplifier section that has frequency characteristics of a band-pass filter and amplifies a signal from the DC level shifter that has been shifted with respect to the DC level, and a control circuit that controls an attenuation of the attenuator based on a signal output from the amplifier section. The control circuit controls the attenuation of the attenuator by changing filter characteristics of the attenuator corresponding to an amplitude of the signal output from the amplifier section so that the signal output from the amplifier section has a constant amplitude even when an amplitude of the received signal has changed.

Claims

1. A receiver circuit comprising:

an attenuator that receives a received signal and attenuates the received signal;

a DC level shifter that shifts a DC level of an attenuated signal from the attenuator;

an amplifier section that has frequency characteristics of a band-pass filter and amplifies a signal from the DC level shifter that has been shifted with respect to the DC level; and

a control circuit that controls an attenuation of the attenuator based on a signal output from the amplifier section,

the control circuit controlling the attenuation of the attenuator by changing filter characteristics of the attenuator corresponding to an amplitude of the signal output from the amplifier section so that the signal output from the amplifier section has a constant amplitude even when an amplitude of the received signal has changed.

2. The receiver circuit as defined in claim 1,

the attenuator having characteristics of a high-pass filter;

and

the control circuit controlling the attenuation of the attenuator by changing a cut-off frequency of the high-pass filter corresponding to the amplitude of the signal output from the amplifier section.

3. The receiver circuit as defined in claim 2,

the control circuit increasing the attenuation of the attenuator in a frequency band of a carrier of the received signal by increasing the cut-off frequency of the high-pass filter as the amplitude of the signal output from the amplifier section increases.

4. The receiver circuit as defined in claim 1,

the control circuit including a charge capacitor provided between a charge node and a first power supply, and a charge transistor provided between the charge node and a second power supply, the control circuit comparing the amplitude of the signal output from the amplifier section with a reference voltage, charging the charge capacitor using the charge transistor based on a comparison result, and outputting a voltage of the charge node to the attenuator as a control voltage.

5. The receiver circuit as defined in claim 4,

the control circuit including a discharge transistor that is provided between the charge node and the first power supply and allows a constant current to flow toward the first power supply.

6. The receiver circuit as defined in claim 5,

a discharge period set based on the constant current that flows through the discharge transistor and a capacitance of the charge capacitor being longer than a transfer period of a first logic level of the received signal that is ASK-modulated.

7. The receiver circuit as defined in claim 1,

the attenuator including:

an attenuation capacitor provided between an input node of the received signal and an output node of the attenuator; and

an attenuation transistor provided between the output node and a first power supply, a control voltage from the control circuit being input to a gate of the attenuation transistor.

8. An amplifier circuit comprising:

a first operational amplifier, an input signal being input to a first input terminal of the first operational amplifier;

a second operational amplifier that is a voltage-follower-connected operational amplifier, an output from the first operational amplifier being input to a first input terminal of the second operational amplifier, and an output from the second operational amplifier being input to a second input terminal of the second operational amplifier and a second input terminal of the first operational amplifier; and

a gain setting section that sets a gain of the amplifier circuit,

when a first bias current that flows through the first operational amplifier is referred to as IB1 and a second bias current that flows through the second operational amplifier is referred to as IB2, the amplifier circuit being provided with frequency characteristics of a band-pass filter by setting the first bias current IB1 to be larger than the second bias current IB2.

9. The amplifier circuit as defined in claim 8,

a low-frequency-side cut-off frequency of the band-pass filter being set based on an output impedance of the second operational amplifier and a load capacitance of an output node of the second operational amplifier, and a high-frequency-side cut-off frequency of the band-pass filter being set based on an output impedance of the first operational amplifier and a load capacitance of an output node of the first operational amplifier.

10. The amplifier circuit as defined in claim 8,

the gain setting section including:

a first capacitor provided between an output of the first operational amplifier and the second input terminal of the first operational amplifier; and

a second capacitor provided between an output of the second operational amplifier and a first power supply.

11. The amplifier circuit as defined in claim 8,

when an offset voltage of the first operational amplifier is referred to as VOF1 and an offset voltage of the second operational amplifier is referred to as VOF2, the offset voltage VOF1 being set to be higher than the offset voltage VOF2.

12. The amplifier circuit as defined in claim 11,

when a gate length and a gate width of differential-pair transistors of the first operational amplifier are respectively referred to as L1 and W1 and a gate length and a gate width of differential-pair transistors of the second operational amplifier are respectively referred to as L2 and W2, L1×

W1 being set to be smaller than L2×

W2.

13. An amplifier circuit comprising:

a first operational amplifier, an input signal being input to a first input terminal of the first operational amplifier;

a second operational amplifier that is a voltage-follower-connected operational amplifier, an output from the first operational amplifier being input to a first input terminal of the second operational amplifier, and an output from the second operational amplifier being input to a second input terminal of the second operational amplifier and a second input terminal of the first operational amplifier; and

a gain setting section that sets a gain of the amplifier circuit,

the second operational amplifier being a rail-to-rail operational amplifier.

14. The amplifier circuit as defined in claim 13,

the second operational amplifier including:

a first differential section that includes a first current-mirror circuit, first differential-pair transistors, and a first current source transistor;

a second differential section that includes a second current-mirror circuit, second differential-pair transistors, and a second current source transistor;

an output section, an output from the first differential section being input to the output section;

a first transistor provided between a first node and a first power supply, the first node being a drain node of one transistor of the first differential-pair transistors of the first differential section, and a third node being connected to a gate of the first transistor, the third node being a drain node of one transistor of the second differential-pair transistors of the second differential section; and

a second transistor provided between a second node and the first power supply, the second node being a drain node of the other transistor of the first differential-pair transistors, and a fourth node being connected to a gate of the second transistor, the fourth node being a drain node of the other transistor of the second differential-pair transistors;

a gate of the one transistor of the first differential-pair transistors being connected to a gate of the other transistor of the second differential-pair transistors; and

a gate of the other transistor of the first differential-pair transistors being connected to a gate of the one transistor of the second differential-pair transistors.

15. The amplifier circuit as defined in claim 13,

the first operational amplifier including a differential section;

the second operational amplifier including a first differential section and a second differential section;

an output of the differential section of the first operational amplifier being connected to first input terminals of the first differential section and the second differential section of the second operational amplifier; and

an output of the first differential section being connected to an output of the second differential section, and the output of the first differential section and the output of the second differential section being connected to a second input terminal of the first differential section and a second input terminal of the second differential section.

16. The amplifier circuit as defined in claim 15,

the differential section of the first operational amplifier including:

a current-mirror circuit;

differential-pair transistors, the input signal being input to a gate of one transistor of the differential-pair transistors, and the output of the first differential section and the output of the second differential section being connected to a gate of the other transistor of the differential-pair transistors; and

a current source transistor that supplies a bias current that flows through the current-mirror circuit and the differential-pair transistors;

the first differential section of the second operational amplifier including;

a first current-mirror circuit that is configured by P-type transistors;

first differential-pair transistors, an output of the differential section being connected to a gate of one N-type transistor of the first differential-pair transistors, and the output of the first differential section and the output of the second differential section being connected to a gate of the other N-type transistor of the first differential-pair transistors; and

a first current source transistor that supplies a bias current that flows through the first current-mirror circuit and the first differential-pair transistors and is configured by an N-type transistor; and

the second differential section of the second operational amplifier including;

a second current-mirror circuit that is configured by N-type transistors;

second differential-pair transistors, the output of the differential section being connected to a gate of one P-type transistor of the second differential-pair transistors, and the output of the first differential section and the output of the second differential section being connected to a gate of the other P-type transistor of the second differential-pair transistors; and

a second current source transistor that supplies a bias current that flows through the second current-mirror circuit and the second differential-pair transistors and is configured by a P-type transistor.

17. The amplifier circuit as defined in claim 16,

the differential-pair transistors of the differential section, the first differential-pair transistors of the first differential section, and the second current-mirror circuit of the second differential section being disposed along a first direction;

and

when a direction perpendicular to the first direction is referred to as a second direction, the second differential-pair transistors of the second differential section being disposed in the second direction with respect to the second current-mirror circuit.

18. The amplifier circuit as defined in claim 17,

an output line of the differential section being provided along the first direction from the differential-pair transistors toward the second current-mirror circuit, and provided along the second direction from the second current-mirror circuit toward the second differential-pair transistors.

19. The amplifier circuit as defined in claim 18,

the gain setting section including:

a first capacitor provided between the output of the first operational amplifier and the second input terminal of the first operational amplifier; and

a second capacitor provided between the output of the second operational amplifier and a first power supply;

when a direction opposite to the first direction is referred to as a third direction and a direction opposite to the second direction is referred to as a fourth direction, the output line of the differential section being provided along the third direction from the second differential-pair transistors toward the first capacitor and connected to one end of the first capacitor; and

a connection line from the other end of the first capacitor being provided along the fourth direction from the first capacitor toward the differential-pair transistors of the differential section.

20. The amplifier circuit as defined in claim 17,

when a direction opposite to the second direction is referred to as a fourth direction, the current source transistor of the differential section being disposed in the fourth direction with respect to the differential-pair transistors, and the first current source transistor of the first differential section being disposed in the fourth direction with respect to the first differential-pair transistors.