Serial Peripheral Interface Switch

• US 20080282017A1
• Filed: 05/09/2007
• Published: 11/13/2008
• Est. Priority Date: 05/09/2007
• Status: Abandoned Application

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Carpenter, Todd L., Westerinen, William J., Schmidt, Shon, Yu, Tse-Ching James, Drake, Stephen Richard, Schmidt, Achim, Preiss, Frank, Schoenfeldt, Stephan
• Application Number:
  US11/746,268
• Publication Number:
  US 20080282017A1
• Time in Patent Office: Days
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 21/82 Protecting input, output or interconnection devices

Abstract

An SPI switch allows selection of a BIOS memory transparent to a Southbridge chipset component. The SPI switch provides address translation to a selected BIOS memory area under the control of a security module processor. The SPI switch also provides command filtering to prevent commands that represent a security risk such as bulk erase commands. Because the SPI switch allows transparent redirection between BIOS programs, booting in different operating modes may be supported without any changes to the basic computer architecture or major chipset components.

Claims

1. A method of managing communications with an SPI slave device in a computer comprising:

disposing a switch coupling a first SPI master to the SPI slave device;

connecting a processor to the switch; and

filtering data from the first SPI master to the SPI slave device under the control of the processor.

2. The method of claim 1, wherein filtering data from the first SPI master to the SPI slave device comprises:

monitoring a request address targeting the SPI slave device; and

substituting an absolute address for use by the SPI slave device.

3. The method of claim 2, wherein substituting the absolute address comprises:

disposing a first and a second basic input/output system (BIOS) in the SPI slave device;

determining when the request address is for the first BIOS;

determining that a condition exists requiring use of a second BIOS; and

substituting the absolute address pointing to the second BIOS.

4. The method of claim 1, wherein filtering data from the first SPI master to the SPI slave device comprises:

monitoring a requested command targeting the slave device;

comparing the requested command to an allowed list; and

allowing the requested command only when the requested command appears on the allowed list.

5. The method of claim 4, wherein the requested command is a bulk erase command.

6. The method of claim 4, further comprising sending allowed list data from the processor to the switch.

7. The method of claim 1, wherein connecting the processor to the switch comprises:

connecting the processor to a data and address interface of the switch; and

connecting the processor to an SPI interface allowing the processor to act as a second SPI master.

8. A serial peripheral interface (SPI) module comprising:

a first SPI port for coupling to an SPI master;

a second SPI port;

an SPI slave coupled to the second SPI port;

a processor; and

a switching apparatus coupled to the processor, the first SPI port, and the second SPI port, the switching apparatus responsive to signals from the processor for selectively coupling the second SPI port to the first SPI port.

9. The SPI module of claim 8, further comprising a logic block for evaluating validity of a command received via the first SPI port, the logic block including an output for blocking an invalid command received via the first SPI port.

10. The SPI module of claim 9, further comprising a register programmable via the processor that stores a list of invalid commands.

11. The SPI module of claim 8, further comprising an address translator for transparently re-addressing messages received at the first SPI port destined for the SPI slave.

12. The SPI module of claim 11, wherein the address translator comprises multiple chip select lines allowing re-addressing across multiple physical SPI slaves.

13. The SPI module of claim 8, wherein the SPI slave is a memory storing executable code for at least one basic input/output system (BIOS).

14. The SPI module of claim 8, further comprising a second bus interface coupled to the processor, the second bus interface one of a low pin count (LPC) bus and a peripheral component interface (PCI) bus.

15. The SPI module of claim 8, wherein the switching apparatus comprises a set of multiplexers for routing SPI control and data signals to the SPI slave from one of the first SPI port and the processor.

16. A computer adapted for use in a restricted mode and an unrestricted mode comprising:

a first processor;

an input/output (I/O) controller coupled to the processor via a main bus;

a memory storing at least one basic input/output system (BIOS) coupled to the I/O controller; and

a switching module coupled between the memory and the I/O controller;

the switching module comprising;

a second processor;

an I/O controller interface;

a memory interface; and

a switch matrix coupled to the second processor, the I/O controller interface, and the memory interface responsive to the second processor for coupling a first BIOS in the memory to the I/O controller when the computer is to be used in the unrestricted mode.

to.

17. The computer of claim 16, wherein the switch matrix further comprises a logic unit that manages address translation for requests received from the I/O controller.

18. The computer of claim 16, wherein the switch matrix further comprises a logic unit that manages command filtering for requests received from the I/O controller.

19. The computer of claim 18, wherein the switch matrix further comprises a register storing a set of requests that are to be filtered when received from the I/O controller.

20. The computer of claim 19, wherein the register is coupled to and receives programming instructions from the second processor.