MEMORY DEVICE AND BUILT IN SELF-TEST METHOD OF THE SAME

• US 20080282119A1
• Filed: 10/23/2007
• Published: 11/13/2008
• Est. Priority Date: 10/24/2006
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hara, Tokumasa, Fujisawa, Shinya, Hashimoto, Shoichiro, Suzuki, Takahiro
• Application Number:
  US11/877,188
• Publication Number:
  US 20080282119A1
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines

Abstract

A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory.

Claims

1. A memory device comprising:

a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item; and

a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory.

2. The device according to claim 1, further comprising, in the chip, an interface which transmits, to the controller, a test command formatted to have an operation bit and a step operation address corresponding to the step item and the parameter start address.

3. The device according to claim 2, further comprising a command analyzer which analyzes the test command transmitted from the interface, and transmits the analyzed test command to the controller.

4. The device according to claim 1, wherein the controller includes an instruction memory which stores a control program for the test step, and a CPU which reads out the control program and executes the step item.

5. The device according to claim 1, wherein the nonvolatile memory has a general area, and a management area limited in at least read more than the general area.

6. The device according to claim 5, wherein the step item and the parameter start address are stored in a first area of the management area.

7. The device according to claim 6, wherein the parameter is stored in a second area of the management area.

8. The device according to claim 1, further comprising a sense amplifier which amplifies write/read data from the nonvolatile memory.

9. The device according to claim 8, further comprising a bus to which the sense amplifier transmits the write/read data.

10. The device according to claim 1, further comprising a buffer which temporarily holds external data, an external address, and an external command.

11. The device according to claim 1, further comprising a power supply circuit which generates a power supply voltage for driving circuits of the device.

12. The device according to claim 1, further comprising a fuse which stores initial data as nonvolatile data.

13. The device according to claim 1, further comprising an oscillator which generates a predetermined oscillation signal.

14. The device according to claim 1, further comprising an error timer which interrupts an operation if an error occurs.

15. A built in self-test method with a memory device including, in the same chip, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller, the method comprising causing the controller to perform, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter.

16. The method according to claim 15, further comprising, before the test step is performed on the nonvolatile memory, causing the device to acquire an operation bit and a step operation address from an externally input command.

17. The method according to claim 16, further comprising, after the operation bit and the step operation address are acquired, causing the controller to acquire a step item and a parameter start address from the nonvolatile memory by using the step operation address.

18. The method according to claim 17, further comprising, after the step item and the parameter start address are acquired, causing the controller to acquire a parameter from the nonvolatile memory by using the parameter start address.

19. The method according to claim 15, further comprising, after the test step is performed on the nonvolatile memory, causing the controller to leave a result of the test step behind in the nonvolatile memory.