SEMICONDUCTOR DEVICE

• US 20080283889A1
• Filed: 04/11/2008
• Published: 11/20/2008
• Est. Priority Date: 05/17/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Matsui, Toshikazu, Ito, Hisanori, Kamei, Satoshi, HARAGUCHI, Keiichi
• Granted Patent: US 8,050,066 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention aims to enhance the reliability of a semiconductor device having first through fourth capacitive elements. The first through fourth capacitive elements are disposed over a semiconductor substrate. A series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between first and second potentials. Lower electrodes of the first and third capacitive elements are respectively formed by a common conductor pattern and coupled to the first potential. Lower electrodes of the second and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and coupled to the second potential. Upper electrodes of the first and second capacitive elements are respectively formed by a common conductor pattern and brought to a floating potential. Upper electrodes of the third and fourth capacitive elements are respectively formed by a conductor pattern of the same layer as the above conductor pattern and brought to a floating potential, but not coupled to the upper electrodes of the first and second capacitive elements by a conductor.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

a first capacitive element, a second capacitive element, a third capacitive element, and a fourth capacitive element which are disposed over the semiconductor substrate,

wherein the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are respectively formed by first and second electrodes opposite to each other via an insulating film interposed therebetween,

wherein the first electrodes of the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are respectively formed by a conductor layer of the same layer,

wherein the second electrodes of the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are respectively formed by a conductor layer of the same layer,

wherein the first electrodes of the first capacitive element and the third capacitive element are electrically coupled to each other through a conductor and coupled to a first potential,

wherein the first electrodes of the second capacitive element and the fourth capacitive element are electrically coupled to each other through a conductor and coupled to a second potential different from the first potential,

wherein the second electrodes of the first capacitive element and the second capacitive element are electrically coupled to each other through a conductor and brought to a floating potential,

wherein the second electrodes of the third capacitive element and the fourth capacitive element are electrically coupled to each other through a conductor and brought to a floating potential, and

wherein the second electrodes of the first capacitive element and the second capacitive element, and the second electrodes of the third capacitive element and the fourth capacitive element are not coupled by a conductor.

2. The semiconductor device according to claim 1, wherein the first electrodes of the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element comprise a first conductor layer formed over the semiconductor substrate, respectively, and the second electrodes of the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element comprise a second conductor layer formed in a layer above or below the first conductor layer, respectively.

3. The semiconductor device according to claim 2, wherein the first conductor layer and the second conductor layer comprise a metal layer respectively.

4. The semiconductor device according to claim 3, wherein the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are of MIM type capacitive elements respectively.

5. The semiconductor device according to claim 4, wherein the second conductor layer is formed in a layer below the first conductor layer.

6. The semiconductor device according to claim 2, wherein the first conductor layer and the second conductor layer comprise a silicon layer respectively.

7. The semiconductor device according to claim 6, wherein the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are of PIP type capacitive elements respectively.

8. The semiconductor device according to claim 7, wherein the second conductor layer is formed in a layer above the first conductor layer.

9. The semiconductor device according to claim 2, wherein each of conductor layers on the lower layer side, of the first conductor layer and the second conductor layer comprises an impurity diffusion layer formed within the semiconductor substrate.

10. The semiconductor device according to claim 9, wherein the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are of MOS type capacitive elements respectively.

11. The semiconductor device according to claim 9, wherein the first electrodes of the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element comprise the impurity diffusion layer formed in the semiconductor substrate, respectively.

12. The semiconductor device according to claim 2, wherein the first electrodes of the first capacitive element and the third capacitive element are respectively formed by a first conductor pattern comprising the first conductor layer, the first electrodes of the second capacitive element and the fourth capacitive element comprise the first conductor layer and are respectively formed by a second conductor pattern electrically separated from the first conductor pattern, the second electrodes of the first capacitive element and the second capacitive element are respectively formed by a third conductor pattern comprising the second conductor layer, and the second electrodes of the third capacitive element and the fourth capacitive element comprise the second conductor layer respectively and are respectively formed by a fourth conductor pattern electrically separated from the third conductor pattern.

13. The semiconductor device according to claim 12, wherein the third conductor pattern and the fourth conductor pattern extend so as to intersect with the first conductor pattern and the second conductor pattern, and the first capacitive element, the second capacitive element, the third capacitive element and the fourth capacitive element are respectively formed in areas where the third conductor pattern and the fourth conductor pattern, and the first conductor pattern and the second conductor pattern cross.

14. The semiconductor device according to claim 1, wherein one of the first potential and the second potential is a source potential and the other thereof is a ground potential.

15. The semiconductor device according to claim 1, wherein the first capacitive element and the second capacitive element are coupled in series, the third capacitive element and the fourth capacitive element are coupled in series, and a series circuit of the first and second capacitive elements and a series circuit of the third and fourth capacitive elements are coupled in parallel between the first potential and the second potential.

16. A semiconductor device comprising:

a circuit formed over a semiconductor substrate, in which series circuits each comprising a pair of first and second capacitive elements are coupled in parallel in plural form between a first potential and a second potential different from the first potential,

wherein the first and second capacitive elements of the series circuits are respectively formed by first and second electrodes opposite to each other via an insulating film interposed therebetween,

wherein the first electrodes of the first capacitive elements of the series circuits are respectively electrically coupled to one another through conductors and coupled to the first potential,

wherein the first electrodes of the second capacitive elements of the series circuits are respectively electrically coupled to one another through conductors and coupled to the second potential,

wherein the second electrodes of the first capacitive elements and the second electrodes of the second capacitive elements in the respective series circuits are electrically coupled to one another through conductors and brought to a floating potential, respectively,

wherein the first electrodes of the first and second capacitive elements of the series circuits are formed by a conductor layer of the same layer,

wherein the second electrodes of the first and second capacitive elements of the series circuits are respectively formed by a conductor layer of the same layer, and

wherein the second electrodes of the first and second capacitive elements of the respective series circuits are not coupled to the second electrodes of the first and second capacitive elements of said other series circuits by conductors.

17. The semiconductor device according to claim 16, wherein the first electrodes of the first and second capacitive elements of the series circuits respectively comprise a first conductor layer formed over the semiconductor substrate, and the second electrodes of the second capacitive elements of the series circuits respectively comprise a second conductor layer formed in a layer above or below the first conductor layer over the semiconductor substrate.

18. The semiconductor device according to claim 17, wherein the first and second capacitive elements are of MIM type, PIP type or MOS type capacitive elements respectively.

19. The semiconductor device according to claim 17, wherein the second conductor layer is formed in a layer below the first conductor layer, and the second electrodes of the first capacitive elements and the second electrodes of the second capacitive elements in the respective series circuits are respectively electrically coupled to one another through a third conductor layer formed in a layer below the second conductor layer over the semiconductor substrate.

20. The semiconductor device according to claim 19, wherein the first capacitive elements and the second capacitive elements of the series circuits are of MIM type capacitive elements respectively, and the MIM type capacitive elements are arranged in array form above a main surface of the semiconductor substrate.

21. The semiconductor device according to claim 16, wherein one of the first potential and the second potential is a source potential and the other thereof is a ground potential.

22. The semiconductor device according to claim 16, wherein the first capacitive elements and the second capacitive elements of the series circuits are of MIM type capacitive elements respectively, and the MIM type capacitive elements are arranged over the entire upper portion of an area in which semiconductor integrated circuits lying over the main surface of the semiconductor substrate are formed.