SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS
First Claim
1. A semiconductor device, comprising:
- a gate stack on a substrate, wherein said gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in said substrate; and
a pair of source/drain regions in said substrate on either side of said channel region, wherein said pair of source/drain regions is in direct contact with said gate dielectric layer, and wherein the lattice constant of said pair of source/drain regions is different than the lattice constant of said channel region.
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Abstract
A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.
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Citations
20 Claims
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1. A semiconductor device, comprising:
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a gate stack on a substrate, wherein said gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in said substrate; and a pair of source/drain regions in said substrate on either side of said channel region, wherein said pair of source/drain regions is in direct contact with said gate dielectric layer, and wherein the lattice constant of said pair of source/drain regions is different than the lattice constant of said channel region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming a semiconductor device, comprising:
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forming a gate stack on a substrate, wherein said gate stack is comprised of a gate electrode above a gate dielectric layer; and forming a pair of source/drain regions on either side of said gate stack and in said substrate to define a channel region in said substrate, wherein said pair of source/drain regions is in direct contact with said gate dielectric layer, and wherein the lattice constant of said pair of source/drain regions is different than the lattice constant of said channel region. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method of forming a semiconductor device, comprising:
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forming a dielectric gate stack placeholder above a substrate; forming a pair of etched-out regions in said substrate and on either side of said dielectric gate stack placeholder; forming a pair of source/drain regions in said pair of etched-out regions to define a channel region in said substrate, wherein said pair of source/drain regions is formed by epitaxially depositing a material layer having a lattice constant different than the lattice constant of said channel region, and wherein said pair of source/drain regions is in direct contact with said dielectric gate stack placeholder; forming an inter-layer dielectric film over said dielectric gate stack placeholder and said pair of source/drain regions; planarizing said inter-layer dielectric film to expose the top surface of said dielectric gate stack placeholder but not the top surface of said pair of source/drain regions; removing said dielectric gate stack placeholder to form a trench in said inter-layer dielectric film; forming a high-k gate dielectric layer at the bottom and along the sidewalls of said trench; and forming a metal gate electrode the portion of said high-k gate dielectric layer at the bottom of said trench and in between the portions of said high-k gate dielectric layer along the sidewalls of said trench. - View Dependent Claims (18, 19, 20)
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Specification