SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS

• US 20080283906A1
• Filed: 05/14/2007
• Published: 11/20/2008
• Est. Priority Date: 05/14/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bohr, Mark T.
• Granted Patent: US 8,450,165 B2
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7378 comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

Claims

1. A semiconductor device, comprising:

a gate stack on a substrate, wherein said gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in said substrate; and

a pair of source/drain regions in said substrate on either side of said channel region, wherein said pair of source/drain regions is in direct contact with said gate dielectric layer, and wherein the lattice constant of said pair of source/drain regions is different than the lattice constant of said channel region.

2. The semiconductor device of claim 1 wherein said gate electrode is a metal gate electrode, and wherein said gate dielectric layer is a high-k gate dielectric layer.

3. The semiconductor device of claim 2 wherein said high-k gate dielectric layer is between said metal gate electrode and said channel region and along the sidewalls of said metal gate electrode.

4. The semiconductor device of claim 3, further comprising:

an inter-layer dielectric film directly adjacent to the portions of said high-k gate dielectric layer along the sidewalls of said metal gate electrode.

5. The semiconductor device of claim 1 wherein said channel region is comprised substantially of silicon atoms, and wherein said pair of source/drain regions is comprised substantially of silicon/germanium having an atomic concentration of germanium atoms in the range of 20-35%.

6. The semiconductor device of claim 5, further comprising:

regions of boron out-diffusion in said substrate and adjacent to the periphery of said pair of source/drain regions.

7. The semiconductor device of claim 1 wherein the lattice constant of said pair of source/drain regions is different than the lattice constant of said channel region by a factor of at least 0.1%.

8. The semiconductor device of claim 1 wherein said pair of source/drain regions have an undercut profile of approximately 55 degrees.

9. A method of forming a semiconductor device, comprising:

forming a gate stack on a substrate, wherein said gate stack is comprised of a gate electrode above a gate dielectric layer; and

forming a pair of source/drain regions on either side of said gate stack and in said substrate to define a channel region in said substrate, wherein said pair of source/drain regions is in direct contact with said gate dielectric layer, and wherein the lattice constant of said pair of source/drain regions is different than the lattice constant of said channel region.

10. The method claim 9 wherein said gate electrode is a metal gate electrode, and wherein said gate dielectric layer is a high-k gate dielectric layer.

11. The method of claim 10 wherein said high-k gate dielectric layer is formed between said metal gate electrode and said channel region and along the sidewalls of said metal gate electrode.

12. The method of claim 11, further comprising:

forming an inter-layer dielectric film directly adjacent to the portions of said high-k gate dielectric layer along the sidewalls of said metal gate electrode.

13. The method of claim 9 wherein said channel region is comprised substantially of silicon atoms, and wherein said pair of source/drain regions is comprised substantially of silicon/germanium having an atomic concentration of germanium atoms in the range of 20-35%.

14. The method of claim 13, further comprising:

forming regions of boron out-diffusion in said substrate and adjacent to the periphery of said pair of source/drain regions.

15. The method of claim 9 wherein the lattice constant of said pair of source/drain regions is different than the lattice constant of said channel region by a factor of at least 0.1%.

16. The method of claim 9 wherein said pair of source/drain regions are formed with an undercut profile of approximately 55 degrees.

17. A method of forming a semiconductor device, comprising:

forming a dielectric gate stack placeholder above a substrate;

forming a pair of etched-out regions in said substrate and on either side of said dielectric gate stack placeholder;

forming a pair of source/drain regions in said pair of etched-out regions to define a channel region in said substrate, wherein said pair of source/drain regions is formed by epitaxially depositing a material layer having a lattice constant different than the lattice constant of said channel region, and wherein said pair of source/drain regions is in direct contact with said dielectric gate stack placeholder;

forming an inter-layer dielectric film over said dielectric gate stack placeholder and said pair of source/drain regions;

planarizing said inter-layer dielectric film to expose the top surface of said dielectric gate stack placeholder but not the top surface of said pair of source/drain regions;

removing said dielectric gate stack placeholder to form a trench in said inter-layer dielectric film;

forming a high-k gate dielectric layer at the bottom and along the sidewalls of said trench; and

forming a metal gate electrode the portion of said high-k gate dielectric layer at the bottom of said trench and in between the portions of said high-k gate dielectric layer along the sidewalls of said trench.

18. The method of claim 17 wherein said dielectric gate stack placeholder is in direct contact with said substrate.

19. The method of claim 17 wherein said pair of etched-out regions are formed with an undercut profile of approximately 55 degrees.

20. The method of claim 17 wherein the lattice constant of said pair of source/drain regions is different than the lattice constant of said channel region by a factor of at least 0.1%.