SELF-ALIGNED AND EXTENDED INTER-WELL ISOLATION STRUCTURE

• US 20080283962A1
• Filed: 05/15/2007
• Published: 11/20/2008
• Est. Priority Date: 05/15/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Luo, Zhijiong, Yang, Haining S., Dyer, Thomas W.
• Granted Patent: US 7,750,429 B2
• Time in Patent Office: Days
• US Class Current: 257/513
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

A pedestal is formed out of the pad layer such that two edges of the pedestal coincide with a border of the wells as implanted. An extended pedestal is formed over the pedestal by depositing a conformal dielectric layer. The area of the extended pedestal is exposed the semiconductor surface below is recessed to a recess depth. Other trenches including at least one intra-well isolation trench are lithographically patterned. After a reactive ion etch, both an inter-well isolation trench and at least one intra-well isolation trench are formed. The width of the inter-well isolation trench may be reduced due to the deeper bottom surface compared to the prior art structures. The boundary between the p-well and the n-well below the inter-well isolation structure is self-aligned to the middle of the inter-well isolation structure.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate having a top surface;

a pair of substantially vertical first trench sidewalls extending from said top surface to a first depth;

a substantially horizontal first trench bottom surface having a first width and located at said first depth from said top surface and adjoined to said pair of substantially vertical first trench sidewalls;

a pair of substantially vertical second trench sidewalls extending from said top surface to a second depth, wherein said first depth is greater than said second depth; and

a substantially horizontal second trench bottom surface having a second width and located at said second depth from said top surface and adjoined to said pair of substantially vertical second trench sidewalls;

wherein said first width is greater than said second width.

2. The semiconductor structure of claim 1, further comprising:

an inter-well isolation trench structure bounded by said pair of substantially vertical first trench sidewalls and said substantially horizontal first trench bottom surface and comprising an insulator material; and

an intra-well isolation trench structure bounded by said pair of substantially vertical second trench sidewalls and said substantially horizontal second trench bottom surface and comprising said insulator material.

3. The semiconductor structure of claim 2, further comprising:

a p-well having a p-well bottom surface located at a third depth from said top surface and abutting one of said pair of substantially vertical first trench sidewalls;

an n-well having an n-well bottom surface located at a fourth depth from said top surface and abutting the other of said pair of substantially vertical first trench sidewalls; and

a substrate layer adjoining said p-well bottom surface and said n-well bottom surface.

4. The semiconductor structure of claim 3, further comprising:

a pair of substantially vertical third trench sidewalls extending from said top surface to said second depth;

a substantially horizontal third trench bottom surface having a second width and located at said second depth from said top surface and adjoined to said pair of substantially vertical third trench sidewalls; and

another intra-well isolation trench structure bounded by said pair of substantially vertical third trench sidewalls and said substantially horizontal third trench bottom surface and comprising said insulator material, wherein said inter-well isolation trench structure is located within said p-well and said another intra-well isolation trench structure is located within said n-well.

5. The semiconductor structure of claim 3, further comprising:

at least one heavily n-doped region abutting said p-well, said top surface, and one of said pair of substantially vertical first trench sidewalls; and

at least one heavily p-doped region abutting said n-well, said top surface, and the other of said pair of substantially vertical first trench sidewalls, wherein each of said at least one heavily n-doped region and said at least one heavily p-doped region has a dopant concentration in the range from about 5.0×

10¹⁹ atoms/cm³ to about 5.0×

10²¹ atoms/cm³.

6. The semiconductor structure of claim 3, wherein said third depth and said fourth depth are greater than said first depth, said p-well abuts one of said pair of substantially vertical first trench sidewalls, said n-well abuts the other of said pair of substantially vertical first trench sidewalls, and said substrate layer abuts said p-well and said n-well.

7. The semiconductor structure of claim 6, wherein said p-well and said n-well abut said substantially horizontal first trench bottom surface.

8. The semiconductor structure of claim 7, further comprising a well boundary at which said p-well adjoins said n-well, wherein said well boundary adjoins said substantially horizontal first trench bottom surface and is self-aligned to the middle of said substantially horizontal first trench bottom surface.

9. The semiconductor structure of claim 8, further comprising:

a vertical p-well to substrate layer interface adjoining said substantially horizontal first trench bottom surface at a first distance from an edge at which one of said pair of substantially vertical first trench sidewalls adjoins said substantially horizontal first trench bottom surface; and

a vertical n-well to substrate layer interface adjoining said substantially horizontal first trench bottom surface at a second distance from another edge at which the other of said pair of substantially vertical first trench sidewalls adjoins said substantially horizontal first trench bottom surface, wherein said first distance is equal to said second distance.

10. The semiconductor structure of claim 3, wherein at least one of said third depth and said fourth depth are less than said first depth, said p-well abuts one of said pair of substantially vertical first trench sidewalls, said n-well abuts the other of said pair of substantially vertical first trench sidewalls, and said substrate layer abuts said p-well, said n-well, said substantially horizontal first trench bottom surface, and at least one of said pair of substantially vertical first trench sidewalls.

11. The semiconductor structure of claim 3, wherein said second depth is less than said first depth, said third depth, and said fourth depth.

12. A method of forming a semiconductor structure comprising:

forming a pedestal on a semiconductor substrate and a p-well and an n-well in said semiconductor substrate, wherein a border of said p-well is coincident with an edge of said pedestal and a border of said n-well is coincident with another edge of said pedestal;

forming a planarization layer over said pedestal and planarizing said planarization layer;

removing said pedestal and exposing a surface of said semiconductor substrate in an inter-well isolation area;

recessing said surface of said semiconductor substrate within said inter-well isolation area;

lithographically patterning and etching said planarization layer in an intra-well isolation area; and

etching an inter-well isolation trench having a first depth and an intra-well isolation trench having a second depth, wherein said first depth is greater than said second depth.

13. The method of claim 12, further comprising:

forming a pedestal layer on a semiconductor substrate;

applying and lithographically patterning a first photoresist and etching said pedestal layer from a first area which is not covered by said first photoresist;

implanting dopants of a first conductivity type into said first area;

applying and lithographically patterning a second photoresist and etching said pedestal layer from a second area which is not covered by said second photoresist, wherein said pedestal is formed out of a remaining portion of said pedestal layer; and

implanting dopants of a second conductivity type into said second area, wherein said second conductivity type is the opposite type of said first conductivity type.

14. The method of claim 13, further comprising:

forming an extended pedestal layer directly on said pedestal, wherein said planarization layer is formed directly on said extended pedestal layer;

exposing a portion of said extended pedestal layer over said pedestal during said planarizing of said planarization layer; and

removing said exposed portion of said extended pedestal layer prior to said recessing of said top surface.

15. The method of claim 12, further comprising filling said recessed surface with a photoresist.

16. The method of claim 12, further comprising filling said inter-well isolation trench and said intra-well isolation trench with a dielectric material.

17. The method of claim 12, wherein said inter-well isolation trench comprises:

a pair of substantially vertical first trench sidewalls extending from said top surface to said first depth; and

a substantially horizontal first trench bottom surface having a first width and located at said first depth from said top surface and adjoined to said pair of substantially vertical first trench sidewalls.

18. The method of claim 17, wherein said intra-well isolation trench comprises:

a pair of substantially vertical second trench sidewalls extending from said top surface to said second depth; and

a substantially horizontal second trench bottom surface having a second width and located at said second depth from said top surface and adjoined to said pair of substantially vertical second trench sidewalls;

wherein said first width is greater than said second width.

19. The method of claim 17, further comprising a substrate layer in said semiconductor substrate, wherein said p-well has a third depth and said n-well has a fourth depth, and said third depth and said fourth depth are greater than said first depth, said p-well abuts one of said pair of substantially vertical first trench sidewalls, said n-well abuts the other of said pair of substantially vertical first trench sidewalls, and said substrate layer abuts said p-well and said n-well.

20. The method of claim 17, further comprising a substrate layer in said semiconductor substrate, wherein said p-well has a third depth and said n-well has a fourth depth, and said third depth and said fourth depth are less than said first depth, said p-well abuts one of said pair of substantially vertical first trench sidewalls, said n-well abuts the other of said pair of substantially vertical first trench sidewalls, and said substrate layer abuts said p-well, said n-well, said pair of substantially vertical first trench sidewalls, and said substantially horizontal first trench bottom surface.