SEMICONDUCTOR DEVICE, SUBSTRATE, EQUIPMENT BOARD, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR CHIP FOR COMMUNICATION

• US 20080284004A1
• Filed: 02/06/2008
• Published: 11/20/2008
• Est. Priority Date: 08/24/2004
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Shimizu, Tatsuo, Shigenami, Kenichi, Sekino, Takeo, Toi, Shinichi, Sukegawa, Shunichi
• Granted Patent: US 7,579,691 B2
• Time in Patent Office: Days
• US Class Current: 257/724
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4943 the connecting portions being staggered
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/162 : the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 21/061 : Two dimensional planar arrays
• CPC Class Codes: H01Q 7/00 : Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop

Abstract

A semiconductor device includes a first substrate having a first surface for mounting an electronic component and a second surface substantially parallel to the first surface. The first substrate includes a first region for mounting the electronic component, a second region including a plurality of first communication units for transmitting and receiving signals to and from a second substrate, input-output circuits disposed on the first region or the second region, the input-out circuits corresponding to the first communication units, and a control circuit for controlling input to and output from the input-output circuits disposed on the first region or the second region of the first substrate. Each of the input-output circuits includes an output circuit for outputting a signal to a second communication unit of the second substrate corresponding to the first communication unit and an input unit for receiving a signal sent from the corresponding second communication unit.

Claims

1. A semiconductor chip for communication disposed on a substrate, comprising:

a planar matrix of communication modules,

wherein each of the communication modules includes,

an antenna for transmitting or receiving radio signals, the antenna being formed of a coiled pattern,

at least one of a transmitter circuit for transmitting a signal to the antenna and a receptor circuit for receiving a signal from the antenna, and

wiring for supplying electrical power and signals to one of the transmitter circuit and the receptor circuit.

2. The semiconductor chip for communication according to claim 1,

wherein each of the communication modules includes both the transmitter circuit and the receptor circuit,

wherein the antenna is connected to an output of the transmitter circuit and an input of the receptor circuit, and

wherein the transmitter circuit and the receptor circuit include terminals that can be individually set to one of an enabled state and a disabled state.

3. The semiconductor chip for communication according to claim 1, further comprising:

a control unit for commonly controlling the communication modules.

4. The semiconductor chip for communication according to claim 1,

wherein at least one of the receptor circuits of the communication modules is an asynchronous receptor circuit and the other receptor circuits are synchronous receptor circuits, and

wherein the semiconductor chip for communication further includes a modulating circuit for modulating a clock signal supplied to the synchronous receptor circuits based on a signal from the asynchronous receptor circuit.