CHIP ASSEMBLY

• US 20080284014A1
• Filed: 03/10/2008
• Published: 11/20/2008
• Est. Priority Date: 03/13/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Lo, Hsin-Jung
• Granted Patent: US 8,193,636 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/11912 : the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/4985 : Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/50 : Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/86 : using tape automated bonding [TAB]
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/0134 : Quaternary Alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A chip assembly includes a semiconductor chip, a bump and an external circuit. The semiconductor chip includes a semiconductor substrate, a transistor in and on the semiconductor substrate, multiple dielectric layers over the semiconductor substrate, a metallization structure over the semiconductor substrate, wherein the metallization structure is connected to the transistor, and a passivation layer over the metallization structure, over the dielectric layers and over the transistor. The bump is connected to the metallization structure through an opening in the passivation layer, wherein the bump includes an adhesion/barrier layer and a gold layer over the adhesion/barrier layer. The external circuit can be connected to the bump using a tape carrier package (TCP), a chip-on-film (COF) package or a chip-on-glass (COG) assembly.

Claims

1. A chip package comprising:

a semiconductor chip comprising a semiconductor substrate comprising silicon, a transistor in or over said semiconductor substrate, a first dielectric layer over said semiconductor substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure is connected to said transistor, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure, over said first and second dielectric layers and over said transistor, and a pad over said semiconductor substrate, wherein said pad is connected to said metallization structure;

a metal bump on said pad, wherein said metal bump comprises an adhesion/barrier layer on said pad and a copper layer with a thickness of between 5 and 30 micrometers on said adhesion/barrier layer;

a flexible circuit film comprising a first polymer layer, a second polymer layer and a copper trace comprising a portion between said first and second polymer layers;

a tin-alloy layer between said copper layer and said copper trace, wherein said tin-alloy layer comprises gold; and

a polymer material enclosing said metal bump.

2. The chip package of claim 1, wherein said tin-alloy layer further comprises silver.

3. The chip package of claim 1, wherein an opening in said passivation layer exposes said pad, and said pad comprises electroplated copper.

4. The chip package of claim 1, wherein an opening in said passivation layer exposes a contact point of said metallization structure, and said pad is on said contact point and comprises a tantalum-containing layer and an aluminum-containing layer on said tantalum-containing layer.

5. The chip package of claim 1, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.

6. The chip package of claim 1, wherein said adhesion/barrier layer comprises a titanium-containing layer having a thickness of between 0.02 and 0.5 μ

m.

7. The chip package of claim 1, wherein said adhesion/barrier layer comprises a tantalum-containing layer having a thickness of between 0.02 and 0.5 μ

m.

8. The chip package of claim 1, wherein said metal bump further comprises a gold layer having a thickness of between 0.2 and 6 micrometers between said copper layer and said tin-alloy layer.

9. The chip package of claim 1, wherein said metal bump further comprises a nickel layer having a thickness of between 0.1 and 5 micrometers between said copper layer and said tin-alloy layer, and a gold layer having a thickness of between 0.2 and 6 micrometers between said nickel layer and said tin-alloy layer.

10. A chip-on-glass (COG) assembly comprising:

a semiconductor chip comprising a semiconductor substrate comprising silicon, a transistor in or over said semiconductor substrate, a first dielectric layer over said semiconductor substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure is connected to said transistor, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure, over said first and second dielectric layers and over said transistor, and a pad over said semiconductor substrate, wherein said pad is connected to said metallization structure;

a metal bump on said pad, wherein said metal bump comprises an adhesion/barrier layer on said pad, a copper layer having a thickness of between 5 and 30 micrometers on said adhesion/barrier layer and a gold layer having a thickness of between 1 and 10 micrometers over said copper layer;

a glass substrate;

a conductive trace between said gold layer and said glass substrate; and

an anisotropic conductive film enclosing said metal bump and between said glass substrate and said semiconductor chip, wherein said anisotropic conductive film comprises multiple conductive particles between said gold layer and said conductive trace.

11. The circuit structure of claim 10, wherein an opening in said passivation layer exposes said pad, and said pad electroplated copper.

12. The circuit structure of claim 10, wherein an opening in said passivation layer exposes a contact point of said metallization structure, and said pad is on said contact point and comprises a tantalum-containing layer and an aluminum-containing layer on said tantalum-containing layer.

13. The circuit structure of claim 10, wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.

14. The circuit structure of claim 10, wherein said metal bump further comprises a nickel layer having a thickness of between 0.1 and 5 micrometers between said copper layer and said gold layer.

15. The circuit structure of claim 10, wherein said conductive trace comprises indium tin oxide (ITO).

16. A chip-on-glass (COG) assembly comprising:

a semiconductor chip comprising a semiconductor substrate comprising silicon, a transistor in or over said semiconductor substrate, a first dielectric layer over said semiconductor substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure is connected to said transistor, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure, over said first and second dielectric layers and over said transistor, and a pad over said semiconductor substrate, wherein said pad is connected to said metallization structure;

a metal bump on said pad, wherein said metal bump comprises an adhesion/barrier layer on said pad, a copper layer having a thickness of between 5 and 30 micrometers on said adhesion/barrier layer and a gold layer having a thickness of between 1 and 10 micrometers over said copper layer;

a glass substrate;

a conductive trace between said gold layer and said glass substrate, wherein said gold layer contacts with said conductive trace; and

a non-conductive film (NCF) enclosing said metal bump and between said glass substrate and said semiconductor chip.

17. The circuit structure of claim 16, wherein an opening in said passivation layer exposes said pad, and said pad comprises electroplated copper.

18. The circuit structure of claim 16, wherein an opening in said passivation layer exposes a contact point of said metallization structure, and said pad is on said contact point and comprises a tantalum-containing layer and an aluminum-containing layer on said tantalum-containing layer.

19. The circuit structure of claim 16, wherein said metal bump further comprises a nickel layer having a thickness of between 0.1 and 5 micrometers between said copper layer and said gold layer.

20. The circuit structure of claim 16, wherein said conductor trace comprises indium tin oxide (ITO).