Reliable metal bumps on top of I/O pads after removal of test probe marks

• US 20080284016A1
• Filed: 07/30/2008
• Published: 11/20/2008
• Est. Priority Date: 02/15/2001
• Status: Active Grant

• Current Assignee: Megica Corporation (Chipbond Technology Corporation)
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lei, Ming-Ta, Lin, Mou-Shiung, Huang, Ching-Cheng, Lin, Chuen-Jye
• Granted Patent: US 8,901,733 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05016 in side view
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05019 being a non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05562 On the entire exposed surface of the internal layer
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.

Claims

1. A wafer comprising:

a silicon substrate;

a dielectric layer over said silicon substrate;

a via in said dielectric layer, wherein said via penetrates through said dielectric layer;

a metal pad on said dielectric layer;

a passivation layer over said dielectric layer and on said metal pad, wherein a first opening in said passivation layer is over said metal pad;

a polymer layer on said passivation layer, wherein said polymer layer has a thickness greater than that of said passivation layer, that of said metal pad, that of said dielectric layer and that of said via; and

a metal bump on said metal pad and on said polymer layer, wherein said metal bump comprises a copper layer over said metal pad and over said polymer layer, a nickel layer on said copper layer, over said metal pad and over said polymer layer, and a solder over an entire top surface of said nickel layer, over said metal pad and over said polymer layer.

2. The wafer of claim 1, wherein said polymer layer is further on said metal pad and in said first opening, and wherein a second opening in said polymer layer is over said metal pad, wherein said metal bump is connected to said metal pad through said second opening.

3. The wafer of claim 1, wherein said polymer layer comprises polyimide.

4. The wafer of claim 1, wherein said via is under said metal pad.

5. The wafer of claim 1, wherein said nickel layer has a thickness between 1 and 10 micrometers.

6. The wafer of claim 1, wherein said metal pad comprises aluminum.

7. A wafer comprising:

a silicon substrate;

a dielectric layer over said silicon substrate;

a via in said dielectric layer, wherein said via penetrates through said dielectric layer;

a metal pad on said dielectric layer;

a passivation layer over said dielectric layer and on said metal pad, wherein a first opening in said passivation layer is over said metal pad;

a polymer layer on said passivation layer, wherein said polymer layer has a thickness greater than that of said passivation layer, that of said metal pad, that of said dielectric layer and that of said via; and

a circuit layer on said metal pad and on said polymer layer, wherein said circuit layer comprises a copper layer over said metal pad and over said polymer layer, a nickel layer on said copper layer, over said metal pad and over said polymer layer, and a gold layer on said nickel layer, over said metal pad and over said polymer layer.

8. The wafer of claim 7, wherein said polymer layer is further on said metal pad and in said first opening, and wherein a second opening in said polymer layer is over said metal pad, wherein said circuit layer is connected to said metal pad through said second opening.

9. The wafer of claim 7, wherein said polymer layer comprises polyimide.

10. The wafer of claim 7, wherein said via is under said metal pad.

11. The wafer of claim 7, wherein said nickel layer has a thickness between 1 and 10 micrometers.

12. The wafer of claim 7, wherein said metal pad comprises aluminum.

13. A wafer comprising:

a silicon substrate;

a dielectric layer over said silicon substrate;

a via in said dielectric layer, wherein said via penetrates through said dielectric layer;

a metal pad on said dielectric layer;

a passivation layer over said dielectric layer and on said metal pad, wherein a first opening in said passivation layer is over said metal pad; and

a circuit layer on said metal pad, wherein said circuit layer comprises a sputtered copper layer over said metal pad, an electroplated nickel layer on said sputtered copper layer and over said metal pad, and a solder over said electroplated nickel layer and over said metal pad.

14. The wafer of claim 13, wherein said circuit layer is further on said passivation layer.

15. The wafer of claim 13 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said metal pad, wherein said circuit layer is connected to said metal pad through said second opening.

16. The wafer of claim 15, wherein said polymer layer is further on said metal pad and in said first opening.

17. The wafer of claim 15, wherein said polymer layer comprises polyimide.

18. The wafer of claim 13, wherein said via is under said metal pad.

19. The wafer of claim 13, wherein said electroplated nickel layer has a thickness between 1 and 10 micrometers.

20. The wafer of claim 13, wherein said metal pad comprises aluminum.