High performance system-on-chip using post passivation process

• US 20080284032A1
• Filed: 08/06/2008
• Published: 11/20/2008
• Est. Priority Date: 03/29/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Granted Patent: US 8,384,189 B2
• Time in Patent Office: Days
• US Class Current: 257/759
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises a metal pad having a top surface with a first region, a second region and a third region between said first and second regions, and wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure, over said first and second dielectric layers and on said first and second regions, wherein an opening in said passivation layer is over said third region, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip;

a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer, that of said first dielectric layer and that of said second dielectric layer;

a patterned metal layer on said first polymer layer and over said passivation layer, wherein said patterned metal layer is connected to said third region through said opening, wherein said patterned metal layer has a thickness greater than that of said first metal layer and that of said second metal layer, and wherein said patterned metal layer comprises a coil on said first polymer layer and over said passivation layer, wherein said coil comprises an electroplated metal layer; and

a second polymer layer over said patterned metal layer.

2. The integrated circuit chip of claim 1, wherein said electroplated metal layer comprises electroplated gold.

3. The integrated circuit chip of claim 1, wherein said first polymer layer comprises polyimide.

4. The integrated circuit chip of claim 1, wherein said passivation layer further comprises an oxide layer under said topmost nitride layer of said integrated circuit chip.

5. The integrated circuit chip of claim 1 further comprising a third metal layer between said first polymer layer and said passivation layer.

6. The integrated circuit chip of claim 5, wherein said third metal layer comprises copper between said first polymer layer and said passivation layer.

7. The integrated circuit chip of claim 5, wherein said third metal layer comprises aluminum between said first polymer layer and said passivation layer.

8. The integrated circuit chip of claim 5, wherein said third metal layer comprises gold between said first polymer layer and said passivation layer.

9. An integrated circuit chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises a metal pad having a top surface with a first region, a second region and a third region between said first and second regions, and wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure, over said first and second dielectric layers and on said first and second regions, wherein an opening in said passivation layer is over said third region, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip;

a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer, that of said first dielectric layer and that of said second dielectric layer;

a patterned metal layer on said first polymer layer and over said passivation layer, wherein said patterned metal layer is connected to said third region through said opening, wherein said patterned metal layer has a thickness greater than that of said first metal layer and that of said second metal layer, and wherein said patterned metal layer comprises a coil on said first polymer layer and over said passivation layer, wherein said coil comprises electroplated copper; and

a second polymer layer over said patterned metal layer.

10. The integrated circuit chip of claim 9, wherein said first polymer layer comprises polyimide.

11. The integrated circuit chip of claim 9, wherein said passivation layer further comprises an oxide layer under said topmost nitride layer of said integrated circuit chip.

12. The integrated circuit chip of claim 9 further comprising a third metal layer between said first polymer layer and said passivation layer.

13. The integrated circuit chip of claim 12, wherein said third metal layer comprises copper between said first polymer layer and said passivation layer.

14. The integrated circuit chip of claim 12, wherein said third metal layer comprises aluminum between said first polymer layer and said passivation layer.

15. The integrated circuit chip of claim 12, wherein said third metal layer comprises gold between said first polymer layer and said passivation layer.

16. An integrated circuit chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises a metal pad having a top surface with a first region, a second region and a third region between said first and second regions, and wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure, over said first and second dielectric layers and on said first and second regions, wherein an opening in said passivation layer is over said third region, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip;

a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer, that of said first dielectric layer and that of said second dielectric layer;

a patterned metal layer on said first polymer layer and over said passivation layer, wherein said patterned metal layer is connected to said third region through said opening, wherein said patterned metal layer has a thickness greater than that of said first metal layer and that of said second metal layer, and wherein said patterned metal layer comprises a coil on said first polymer layer and over said passivation layer, wherein said coil comprises gold; and

a second polymer layer over said patterned metal layer.

17. The integrated circuit chip of claim 16 further comprising a third metal layer between said first polymer layer and said passivation layer.

18. The integrated circuit chip of claim 17, wherein said third metal layer comprises copper between said first polymer layer and said passivation layer.

19. The integrated circuit chip of claim 17, wherein said third metal layer comprises aluminum between said first polymer layer and said passivation layer.

20. The integrated circuit chip of claim 17, wherein said third metal layer comprises gold between said first polymer layer and said passivation layer.