Vertical system integration

• US 20080284611A1
• Filed: 06/21/2008
• Published: 11/20/2008
• Est. Priority Date: 08/08/2002
• Status: Abandoned Application

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn J.
• Application Number:
  US12/143,772
• Publication Number:
  US 20080284611A1
• Time in Patent Office: Days
• US Class Current: 340/815.4
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/118 : Masterslice integrated circuits
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1463 : Pixel isolation structures
• CPC Class Codes: H01L 27/14643 : Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 29/40114 : the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 : Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04W 4/80 : Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/30 : DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Claims

1. A method of using a stacked integrated circuit comprising:

placing the stacked integrated circuit in proximity to at least one other stacked integrated circuit, thereby causing wireless communication between the stacked integrated circuits to occur.

2. The method of claim 1, wherein one of the stacked integrated circuits comprises a wireless interconnection processor, comprising the wireless interconnection processor interogating at least one other stacked integrated circuit in proxmity thereto.

3. The method of claim 2, wherein said at least one other stacked integrated circuit comprises a visual indicator, comprising activating the visual indicator in response to said interogating.

4. The method of claim 3, comprising a user recognizing activation of the visual indicator and in response thereto placing the at least one stacked integrated circuit in operating relation to an electronic device.

5. The method of claim 1, wherein at least one of the stacked integrated circuits comprises IC devices, said IC devices comprising at least one of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

6. The method of claim 5, wherein the IC devices comprise at least two of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

7. The method of claim 5, wherein the IC devices comprise all of the following:

transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

8. The method of claim 1, wherein, for at least one of the stacked integrated circuits, the stacked integrated circuit is made without fabrication of a circuit layer specific to the function of the particular stacked integrated circuit.

9. The method of claim 1, wherein, for at least one of the stacked integrated circuits, fewer than all of the circuit layers are fabricated for the specific function of the particular stacked integrated circuit.

10. The method of claim 1, wherein at least one of the stacked integrated circuits comprises a plurality of circuit layers, IC device fabrication having been performed on the backside of one or more of said circuit layers.

11. The method of claim 1, wherein at least one of the stacked integrated circuits comprises a plurality of circuit layers, the circuit layers having been bonded using bonding layers made from two or more metal films one of which has a lower melting temperature and which will diffuse with an immediately adjacent film.

12. The method of claim 1, wherein, for at least one of the stacked integrated circuits, an application-specific function of the stacked integrated circuit derives from the choice and quantity of circuit layers chosen from previously-fabricated, non-application-specific circuit layers.

13. The method of claim 1, wherein at least one of the stacked integrated circuits comprises an IC substrate and interconnections formed between circuitry on a frontside of the IC substrate with the circuitry formed on a backside of the IC substrate.

14. The method of claim 1, wherein at least one of the stacked integrated circuits comprises a stacked programmable logic device having at least one of a programmable gate circuit layer and a memory circuit layer.