PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES USING EXTERNALLY HEATED PHASE CHANGE MATERIAL

• US 20080285335A1
• Filed: 05/28/2008
• Published: 11/20/2008
• Est. Priority Date: 02/07/2007
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Park, Byeongju, Krusin-Elbaum, Lia, Iyer, Subramanian S., Newns, Dennis M., Kim, Deok-Kee, Elmegreen, Bruce G.
• Application Number:
  US12/127,909
• Publication Number:
  US 20080285335A1
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/008 Write by generating heat in the surroundings of the memory material, e.g. thermowrite
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/253 having three or more terminals, e.g. transistor-like devices
• CPC Class Codes: H10N 70/821 Device geometry
• CPC Class Codes: H10N 70/8613 Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

A programmable phase change material (PCM) structure includes a heater element formed at a transistor gate level of a semiconductor device, the heater element further including a pair of electrodes connected by a thin wire structure with respect to the electrodes, the heater element configured to receive programming current passed therethrough, a layer of phase change material disposed on top of a portion of the thin wire structure, and sensing circuitry configured to sense the resistance of the phase change material.

Claims

1. A programmable phase change material (PCM) structure, comprising:

a heater element formed at a transistor gate level of a semiconductor device;

the heater element further including a pair of electrodes connected by a thin wire structure with respect to the electrodes, the heater element configured to receive programming current passed therethrough;

a layer of phase change material disposed on top of a portion of the thin wire structure; and

sensing circuitry configured to sense the resistance of the phase change material.

2. The programmable PCM structure of claim 1, where the sensing circuitry further comprises an input node coupled to an extended portion of the phase change material not in direct contact with the thin wire structure.

3. The programmable PCM structure of claim 2, wherein the sensing circuitry further comprises a reference resistor coupled to the input node such that the input node is discharged to ground when a portion of the phase change material formed on the thin wire structure is programmed to a high resistance state.

4. The programmable PCM structure of claim 3, wherein the input node is maintained at a logic high voltage through coupling to a heater power source when a portion of the phase change material formed on the thin wire structure is programmed to a low resistance state.

5. A non-volatile, programmable phase change material (PCM) memory array, comprising:

a plurality of memory cells arranged in rows and columns, with each memory cell comprising a heater element formed at a transistor gate level of a semiconductor device;

the heater element further including a pair of electrodes connected by a thin wire structure with respect to the electrodes the heater element configured to receive programming current passed therethrough;

a layer of phase change material disposed on top of a portion of the thin wire structure; and

sensing circuitry configured to sense the resistance of the phase change material.

6. The memory array of claim 5, wherein the sensing circuitry further comprises:

a program line corresponding to each column, the program line configured for selective coupling to an adjustable power source;

a programming transistor for each cell, the programming transistor connected in series between the cell heater element and the program line, wherein the programming transistor is activated by a signal applied to a gate line corresponding to a given row; and

a sense line corresponding to each column, the sense line configured for selective coupling to a fixed power source;

wherein an extended portion of the phase change material not in direct contact with the thin wire structure is configured to receive a sensing voltage applied thereto, the sensing voltage originating from the fixed power source.

7. The memory array of claim 6, wherein each cell further comprises a sense transistor connected in series between the extended portion of the phase change material and the sense line, wherein the sense transistor is activated by a signal applied to the gate line of the cell.

8. The memory array of claim 6, wherein each row further comprises a peripherally located sense transistor which selectively connects each of the heater elements in the row to ground, wherein the sense transistor is activated by a signal applied to the gate line of the row.

9. The memory array of claim 6, wherein a selected cell is programmed through application of a programming voltage to the associated program line and pulsing of the gate line coupled to the programming transistor of the cell, wherein the magnitude and duration of the gate line pulse is selected between one of:

a lower magnitude and slower ramp down, and a larger magnitude and faster ramp down, depending upon the logical state of the bit to be programmed into the cell.

10. The memory array of claim 9, wherein a selected cell is sensed through application of a sensing voltage to the associated sense line and pulsing of the gate line coupled to the programming transistor of the cell, wherein the magnitude of current sensed on the programming line corresponds to the logical state of the selected cell, and wherein the sensing voltage is less than a threshold level of the programming voltage.

11. The memory array of claim 5, wherein the sensing circuitry further comprises:

a program line corresponding to each column, the program line configured for selective coupling to an adjustable power source;

a programming transistor for each cell, the programming transistor connected in series between the cell heater element and ground, wherein the programming transistor is activated by a signal applied to a gate line corresponding to a given row; and

a reference resistor connected in parallel with the program line, and in series between an extended portion of the phase change material of each cell of the column and a power source node of the adjustable power source;

wherein the resistance value of the reference resistor is selected so as to apply a sensing voltage to the phase change material of each cell of the column.

12. The memory array of claim 11, wherein the resistance value, r, of the reference resistor is selected in accordance with the expression:

r<

(Rv+Rh/2)/N;

wherein Rv represents a low resistance value of the phase change material in a crystalline state, Rh represents the resistance value of the heater element, and N is the total number of rows in the array.

13. The memory array of claim 12, wherein r is from about 1 to about 100 ohms.

14. The memory array of claim 11, wherein a selected cell is programmed through application of a programming voltage to the associated program line and pulsing of the gate line coupled to the programming transistor of the cell, wherein the magnitude and duration of the gate line pulse is selected between one of:

a lower magnitude and slower ramp down, and a larger magnitude and faster ramp down, depending upon the logical state of the bit to be programmed into the cell.

15. The memory array of claim 14, wherein a selected cell is sensed through pulsing of the gate line coupled to the programming transistor of the cell, wherein the magnitude of current through the sense resistor corresponds to the logical state of the selected cell, and wherein the sensing voltage is less than a threshold level of the programming voltage.