MEASURING THRESHOLD VOLTAGE DISTRIBUTION IN MEMORY USING AN AGGREGATE CHARACTERISTIC

• US 20080285351A1
• Filed: 11/26/2007
• Published: 11/20/2008
• Est. Priority Date: 05/14/2007
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Shlick, Mark, Lasser, Menahem
• Granted Patent: US 8,073,648 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A threshold voltage distribution of a set of storage elements in a memory device is measured by sweeping a control gate voltage while measuring a characteristic of the set of storage elements as a whole. The characteristic indicates how many of the storage elements meet a given condition, such as being in a conductive state. For example, the characteristic may be a combined current, voltage or capacitance of the set which is measured at a common source of the set. The control gate voltage can be generated internally within a memory die. Similarly, the threshold voltage distribution can be determined internally within the memory die. Optionally, storage elements which become conductive can be locked out, such as by changing a bit line voltage, so they no longer contribute to the characteristic. New read reference voltages are determined based on the threshold voltage distribution to reduce errors in future read operations.

Claims

1. A method for operating a memory device, comprising:

generating a voltage sweep internally from within a memory die, the memory die includes a set of storage elements and an associated word line;

applying the voltage sweep to the word line;

measuring a characteristic of the set of storage elements while applying the voltage sweep; and

determining a threshold voltage distribution of the storage elements based on the characteristic.

2. The method of claim 1, wherein:

the voltage sweep is generated by control circuitry which is internal to the memory die, without using external test equipment.

3. The method of claim 1, wherein:

the voltage sweep is generated by a digital-to-analog converter which is internal to the memory die, in response to a series of code words which are provided to the digital-to-analog converter.

4. The method of claim 1, wherein:

the voltage sweep comprises a continuous voltage sweep.

5. The method of claim 1, wherein:

the voltage sweep comprises different voltages which are applied to the word line as discrete values.

6. The method of claim 1, wherein:

the characteristic comprises a voltage or capacitance.

7. A method for operating a memory device, comprising:

applying different voltages to a word line which is associated with a set of storage elements, the word line and set of storage elements are provided on a memory die;

measuring, within the memory die, a characteristic of the set of storage elements while applying the different voltages; and

determining, within the memory die, a threshold voltage distribution of the storage elements based on the characteristic.

8. The method of claim 7, wherein:

the threshold voltage distribution is determined by control circuitry which is internal to the memory device, without using external test equipment or an external host.

9. The method of claim 7, wherein:

the different voltages are generated internally within the memory device.

10. The method of claim 7, wherein:

the characteristic comprises a voltage.

11. The method of claim 7, wherein:

the characteristic comprises a capacitance.

12. A method for operating a memory device, comprising:

applying different voltages to a word line which is associated with a set of storage elements;

measuring a characteristic of the set of storage elements while applying the different voltages;

locking out storage elements which become conductive while applying the different voltages, so that the locked out storage elements no longer contribute to the characteristic; and

determining a threshold voltage distribution of the storage elements based on the characteristic.

13. The method of claim 12, wherein:

each of the storage elements is associated with a respective NAND string, and the locked out storage elements are locked out by changing bit line voltages of the associated NAND strings.

14. The method of claim 12, wherein:

the locked out storage elements are no longer conductive.

15. The method of claim 12, further comprising:

setting at least one reference voltage for reading the storage elements in a read operation based on rates of change of the characteristic with respect to the different voltages.

16. The method of claim 12, wherein:

the characteristic is measured at a point which is coupled to each of the storage elements in the set.

17. The method of claim 12, wherein:

the characteristic comprises voltage.

18. The method of claim 12, wherein:

the characteristic comprises capacitance.

19. The method of claim 12, wherein:

the characteristic comprises current.

20. A method for operating a memory device, comprising:

sweeping a voltage applied to a word line which is associated with a set of storage elements, each of the storage elements is associated with a respective NAND string;

identifying storage elements in the set which become conductive during the sweeping; and

changing bit line voltages of NAND strings which are associated with the identified storage elements.

21. The method of claim 20, wherein:

the changing the bit line voltages which are associated with the identified storage elements comprises grounding the bit line voltages which are associated with the identified storage elements.

22. The method of claim 20, wherein:

the voltage is swept in a continuous sweeping.

23. The method of claim 20, wherein:

the voltage is swept in a staircase sweeping.

24. The method of claim 20, further comprising:

measuring a characteristic of the set of storage elements during the sweeping; and

determining a threshold voltage distribution of the storage elements based on the characteristic.

25. The method of claim 24, wherein:

the changing the bit line voltages of the NAND strings which are associated with the identified storage elements results in the identified storage elements no longer contributing to the characteristic.

26. A storage system, comprising:

a set of storage elements and an associated word line formed on a memory die of a memory device; and

at least one control circuit in communication with the set of storage elements and the word line, the at least one control circuit is formed on the memory die, generates a voltage sweep internally from within the memory die, applies the voltage sweep to the word line, measures a characteristic of the set of storage elements while applying the voltage sweep, and determines a threshold voltage distribution of the storage elements based on the characteristic.

27. The storage system of claim 26, wherein:

the voltage sweep is generated by the at least one control circuit without using external test equipment.

28. The storage system of claim 26, wherein:

the at least one control circuit includes a digital-to-analog converter which generates the voltage sweep in response to a series of code words which are provided to the digital-to-analog converter.

29. The storage system of claim 26, wherein:

the voltage sweep comprises a continuous voltage sweep.

30. The storage system of claim 26, wherein:

the voltage sweep comprises different voltages which are applied to the word line as discrete values.

31. The storage system of claim 26, wherein:

the characteristic comprises a voltage or capacitance.

32. A storage system, comprising:

a set of storage elements and an associated word line formed on a memory die of a memory device; and

at least one control circuit in communication with the set of storage elements and the word line, the at least one control circuit is formed on the memory die, applies different voltages to the word line, measures, within the memory die, a characteristic of the set of storage elements while applying the different voltages, and determines, within the memory die, a threshold voltage distribution of the storage elements based on the characteristic.

33. The storage system of claim 32, wherein:

the threshold voltage distribution is determined by the at least one control circuit without using external test equipment or an external host.

34. The storage system of claim 32, wherein:

the different voltages are generated internally within the memory device.

35. The storage system of claim 32, wherein:

the characteristic comprises a voltage.

36. The storage system of claim 32, wherein:

the characteristic comprises a capacitance.

37. A storage system, comprising:

a set of storage elements and an associated word line in a memory device; and

at least one control circuit in communication with the set of storage elements, the at least one control circuit applies different voltages to the word line, measures a characteristic of the set of storage elements while applying the different voltages, locks out storage elements which become conductive while applying the different voltages, so that the locked out storage elements no longer contribute to the characteristic, and determines a threshold voltage distribution of the storage elements based on the characteristic.

38. The storage system of claim 37, wherein:

each of the storage elements is associated with a respective NAND string, and the locked out storage elements are locked out by changing bit line voltages of the associated NAND strings.

39. The storage system of claim 37, wherein:

the locked out storage elements are no longer conductive.

40. The storage system of claim 37, wherein:

at least one reference voltage is set, based on the threshold voltage distribution, for reading the storage elements in a read operation.

41. The storage system of claim 37, wherein:

at least one reference voltage is set for reading the storage elements in a read operation based on rates of change of the characteristic with respect to the different voltages.

42. The storage system of claim 37, wherein:

the characteristic is measured at a point which is coupled to each of the storage elements in the set.

43. The storage system of claim 37, wherein:

the characteristic comprises voltage or capacitance.

44. A storage system, comprising:

a set of storage elements in a memory device, each of the storage elements is associated with a respective NAND string; and

at least one control circuit in communication with the set of storage elements, the at least one control circuit sweeps a voltage applied to a word line which is associated with the set of storage elements, identifies storage elements in the set which become conductive during the sweeping, and changes bit line voltages of NAND strings which are associated with the identified storage elements.

45. The storage system of claim 44, wherein:

the voltage is swept in a continuous sweeping.

46. The storage system of claim 44, wherein:

the voltage is swept in a staircase sweeping.

47. The storage system of claim 44, wherein:

the at least one control circuit measures a characteristic of the set of storage elements during the sweeping, and a threshold voltage distribution of the storage elements is determined based on the characteristic.

48. The storage system of claim 47, wherein:

the characteristic comprises a combined current flowing through a plurality of the storage elements during the sweeping.

49. The storage system of claim 47, wherein:

the changes to the bit line voltages of the NAND strings which are associated with the identified storage elements results in the identified storage elements no longer contributing to the characteristic.

50. The storage system of claim 47, wherein:

the changes to the bit line voltages of the NAND strings which are associated with the identified storage elements comprises grounding the bit line voltages of the NAND strings which are associated with the identified storage elements.