Semiconductor memory device employing clamp for preventing latch up
First Claim
Patent Images
1. A semiconductor memory device comprising:
- means for precharging and equalizing a pair of bit lines; and
means for generating a control signal which controls enable and disable of the precharging/equalizing means,wherein the control signal generating means includes a clamping means to clamp its source voltage to a voltage level lower than that of its bulk bias.
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Abstract
A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.
25 Citations
22 Claims
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1. A semiconductor memory device comprising:
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means for precharging and equalizing a pair of bit lines; and means for generating a control signal which controls enable and disable of the precharging/equalizing means, wherein the control signal generating means includes a clamping means to clamp its source voltage to a voltage level lower than that of its bulk bias. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor memory device comprising:
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a sense amplifier, connected to a pair of bit lines, for amplifying electric potential difference of the bit line pair; a sense amplifier driver which includes means for precharging and equalizing a driving voltage line of the sense amplifier and drives the sense amplifier driving voltage line; and a control signal generating means which produces a control signal to control enable and disable of the precharging/equalizing means in the sense amplifier driver, wherein the control signal generating means includes a clamping means to clamp its source voltage to a voltage level lower than that of its bulk bias. - View Dependent Claims (7, 8, 9, 10)
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11. A semiconductor memory device comprising:
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a pair of data lines; means for driving an input signal to the data line pair; means for precharging and equalizing the data line pair; a first clamping means for clamping a source voltage of the data line driving means to a voltage level lower than that of a bulk bias of the data line driving means; and a second clamping means for clamping a source voltage of the precharging/equalizing means to a voltage level lower than that of a bulk bias of the precharging/equalizing means. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A semiconductor memory device comprising:
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a pair of local data input/output (I/O) lines and a pair of segment data input/output (I/O) lines; an isolation switching means for controlling transmission between the segment data I/O line pair and the local data I/O line pair; means for equalizing the segment data I/O line pair and the local data I/O line pair; and means for generating a control signal used to control enable and disable of the equalizing means, wherein the control signal generating means includes a clamping means to clamp its source voltage to a voltage level lower than that of its bulk bias. - View Dependent Claims (19, 20, 21, 22)
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Specification