MULTI-WAFER 3D CAM CELL
First Claim
1. A multi-wafer CAM cell comprising:
- at least one compare element located in a first structure which is vertically stacked on top of, or below, at least one storage element located in a second structure, said at least one compare element and said at least one storage element present in separate wafers and are interconnected by at least one vertically conductive filled via hole.
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Accused Products
Abstract
A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.
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Citations
20 Claims
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1. A multi-wafer CAM cell comprising:
at least one compare element located in a first structure which is vertically stacked on top of, or below, at least one storage element located in a second structure, said at least one compare element and said at least one storage element present in separate wafers and are interconnected by at least one vertically conductive filled via hole. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A multi-wafer CAM cell comprising
at least one compare element including a plurality of first transistors arranged in a 9T configuration located in a first structure which is vertically stacked on top of at least one storage element including a plurality of second transistors arranged in a 6T configuration located in a second structure, said at least one compare element and said at least one storage element are present in separate wafers and are interconnected by at least one vertically conductive filled via hole.
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13. A method of forming a multi-wafer CAM cell comprising:
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providing a first structure including a plurality of first transistors located upon and within a surface of a first active semiconductor layer; providing a second structure including a plurality of second transistors located upon and within a surface of a second active semiconductor layer; bonding a surface of said second structure to a surface of said first structure to provide a bonded structure in which the plurality of first transistors are located above the plurality of second transistors; and forming at least one vertically conductive filled via to connect said plurality of first transistors to said plurality of second transistors. - View Dependent Claims (14, 16, 17, 18, 19, 20)
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15. The method 13 wherein said providing first structure includes the steps of attaching a handling substrate to a surface of a dielectric material that encapsulates said plurality of first transistors.
Specification