MULTI-PROCESSOR CONTROL DEVICE AND METHOD

• US 20080288796A1
• Filed: 05/16/2008
• Published: 11/20/2008
• Est. Priority Date: 05/18/2007
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Semiconductor Technology Academic Research Center
• Inventors: Kondo, Masaaki, Nakamura, Hiroshi, Watanabe, Ryo, Nanya, Takashi
• Granted Patent: US 8,069,357 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/32 Means for saving power

Abstract

A multi-processor control device according to an example of the invention comprises a cooperative control unit which determines priorities of requests issued from processors to a shared resource which are used to suppress a total power consumption of the processors within a range in which performance constraints of programs executed by the processors are satisfied, and determines a frequency of each of the processors so as to suppress the total power consumption within the range in which the performance constraint of the each program is satisfied, a first control unit which issues requests from the processors to the shared resource in accordance with priorities determined by the cooperative control unit, and a second control unit which controls the frequency of each of the processors in accordance with the frequency determined by the cooperative control unit.

Claims

1. A multi-processor control device comprising:

a cooperative control unit which determines priorities of requests issued from a plurality of processors to a shared resource of the plurality of processors which are used to suppress at least one of a total power consumption and a total energy consumption of the plurality of processors within a range in which performance constraints of programs executed by the plurality of processors are satisfied, and determines at least one of a frequency and a power supply voltage of each of the plurality of processors so as to suppress the at least one of the total power consumption and the total energy consumption within the range in which the performance constraint of the each program is satisfied;

a first control unit which issues requests from the plurality of processors to the shared resource in accordance with priorities determined by the cooperative control unit; and

a second control unit which controls at least one of the frequency and the power supply voltage of each of the plurality of processors in accordance with the at least one of the frequency and the power supply voltage determined by the cooperative control unit.

2. A device according to claim 1, wherein the cooperative control unit sets a priority of a request from a processor which executes a program with high emergence to be higher than a priority of a request from a processor which executes a program with low emergence.

3. A device according to claim 2, wherein the cooperative control unit sets at least one of a frequency and a power supply voltage of a processor whose priority of a request has been increased to be lower than that when no priority control is performed.

4. A device according to claim 3, wherein the cooperative control unit monitors an actual state of contention from the plurality of processors to the shared resource and executes feedback control to make match the actual state of contention with the priorities,

monitors a progress state of the each program, and

performs feedback control for each processor which executes the each program so as to decrease at least one of a frequency and a power supply voltage when a progress state of the each program comes to an end earlier than a prediction result predicted on the basis of a performance prediction model and increase the at least one of the frequency and the power supply voltage when the progress state of the each program is expected not to be in time with the prediction result.

5. A device according to claim 3, wherein the cooperative control unit controls priorities of requests from the plurality of processors such that each of frequencies of the plurality of processors is included within a target range.

6. A multi-processor control method comprising:

executing a control algorithm which determines priorities of requests issued from a plurality of processors to a shared resource of the plurality of processors which are used to suppress at least one of a total power consumption and a total energy consumption of the plurality of processors within a range in which performance constraints of programs executed by the plurality of processors are satisfied, and at least one of a frequency and a power supply voltage of each of the plurality of processors; and

issuing requests from the plurality of processors to the shared resource in accordance with priorities determined by the control algorithm and controlling the at least one of the frequency and the power supply voltage of each of the plurality of processors in accordance with the at least one of the frequency and the power supply voltage determined by the control algorithm.

7. A method according to claim 6, wherein the control algorithm sets a priority of a request from a processor which executes a program with high emergence to be higher than a priority of a request from a processor which executes a program with low emergence.

8. A method according to claim 7, wherein the control algorithm sets at least one of a frequency and a power supply voltage of a processor whose priority of a request has been increased to be lower than that when no priority control is performed.

9. A method according to claim 8, wherein the control algorithm monitors an actual state of contention from the plurality of processors to the shared resource and executes feedback control to make match the actual state of contention with the priorities,

monitors a progress state of the each program, and

performs feedback control for each processor which executes the each program so as to decrease at least one of a frequency and a power supply voltage when a progress state of the each program comes to an end earlier than a prediction result predicted on the basis of a performance prediction model and increase the at least one of the frequency and the power supply voltage when the progress state of the each program is expected not to be in time with the prediction result.

10. A method according to claim 8, wherein the control algorithm controls priorities of requests from said plurality of processors such that each of frequencies of the plurality of processors is included falls within a target range.