Nonvolatile charge trap memory device having <100> crystal plane channel orientation

• US 20080290398A1
• Filed: 09/26/2007
• Published: 11/27/2008
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ramkumar, Krishnaswamy, Levy, Sagy, Polishchuk, Igor
• Granted Patent: US 7,880,219 B2
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with <100> crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.

Claims

1. A nonvolatile charge trap memory device, comprising:

a source region and a drain region formed in an active region;

a channel region having a channel length with <

100>

crystal plane orientation between the source region and the drain region; and

a gate stack disposed above the channel region.

2. The nonvolatile charge trap memory device of claim 1, wherein the gate stack is a SONOS-type gate stack.

3. The nonvolatile charge trap memory device of claim 1, wherein the active region comprises silicon.

4. The nonvolatile charge trap memory device of claim 3, wherein the source region and the drain region have an N-type conductivity, and wherein the channel region has a P-type conductivity.

5. The nonvolatile charge trap memory device of claim 4, wherein the gate stack comprises a dielectric charge-trapping layer.

6. A nonvolatile charge trap memory device, comprising:

an isolation structure formed in a substrate;

an active region formed in the substrate and adjacent to the isolation structure;

a channel region formed in the active region, wherein the channel region has a channel length with <

100>

crystal plane orientation;

a source region and a drain region formed in the active region, wherein the channel region is between the source region and the drain region; and

a gate stack disposed above the channel region.

7. The nonvolatile charge trap memory device of claim 6, wherein the isolation structure comprises a liner oxide having approximately equal thickness on a sidewall and a bottom surface of the isolation structure.

8. The nonvolatile charge trap memory device of claim 6, wherein the gate stack is a SONOS-type gate stack.

9. The nonvolatile charge trap memory device of claim 6, wherein the active region comprises silicon.

10. The nonvolatile charge trap memory device of claim 9, wherein the source region and the drain region have an N-type conductivity, and wherein the channel region has a P-type conductivity.

11. The nonvolatile charge trap memory device of claim 10, wherein the gate stack comprises a dielectric charge-trapping layer.

12. A nonvolatile charge trap memory device, comprising:

a channel region formed in an active region, wherein the channel region has a top surface having <

100>

crystal plane orientation and a sidewall surface having <

100>

crystal plane orientation;

an isolation structure adjacent to the sidewall of the channel region, wherein the top surface of the channel region is above a top surface of the isolation structure; and

a gate stack disposed over the top surface and the sidewall surface of the channel region.

13. The nonvolatile charge trap memory device of claim 12, wherein the gate stack comprises a tunnel dielectric layer on the top surface and the sidewall surface of the channel region, and wherein the tunnel dielectric layer has a uniform thickness.

14. The nonvolatile charge trap memory device of claim 12, wherein the gate stack is a SONOS-type gate stack.

15. The nonvolatile charge trap memory device of claim 12, wherein the active region comprises silicon.

16. The nonvolatile charge trap memory device of claim 15, wherein the gate stack comprises a dielectric charge-trapping layer.

17. A method of fabricating a nonvolatile charge trap memory device, comprising:

forming an isolation region and an active region in a substrate, wherein the active region is adjacent to the isolation region;

forming a gate stack above the active region; and

forming a source region and a drain region in the active region and on other side of the gate stack to provide a channel region in the active region, wherein the channel region has a channel length with <

100>

crystal plane orientation between the source region and the drain region.

18. The method of claim 17, wherein the gate stack is a SONOS-type gate stack.

19. The method of claim 18, wherein the active region comprises silicon.

20. The method 19, wherein the source region and the drain region have an N-type conductivity, and wherein the channel region has a P-type conductivity.