MICROELECTRONIC ASSEMBLY AND METHOD FOR FORMING THE SAME

• US 20080290480A1
• Filed: 08/05/2008
• Published: 11/27/2008
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Gogoi, Bishnu P.
• Granted Patent: US 7,723,821 B2
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A microelectronic assembly and a method for forming the same are provided. The method includes forming first and second lateral etch stop walls (44, 46) in a semiconductor substrate (20) having first and second opposing surfaces (22, 24). An inductor (56) is formed on the first surface (22) of the semiconductor substrate (20) and a hole (60) is formed through the second surface (24) of the substrate (20) to expose the substrate (20) between the first and second lateral etch stop walls (44, 46). The substrate (20) is isotropically etched between the first and second lateral etch stop walls (44, 46) through the etch hole (60) to create a cavity 62) within the semiconductor substrate (20). A sealing layer (70) is formed over the etch hole (60) to seal the cavity (62).

Claims

1. A microelectronic assembly, comprising:

a semiconductor substrate having first and second trenches formed thereon;

an etch stop layer on the substrate and in the first and second trenches forming first and second etch stop walls, the substrate and the etch stop layer jointly forming a cavity below the etch stop layer and between the first and second etch stop walls with an etch hole interconnecting the cavity and a first surface of the semiconductor substrate, the etch stop layer comprising an etch stop material;

an inductor on a second surface of the semiconductor substrate, at least a portion of the inductor being positioned over the cavity in the semiconductor substrate; and

a sealing layer formed over the etch hole at the first surface of the semiconductor substrate.

2. The microelectronic assembly of claim 1, wherein the first surface of the semiconductor substrate opposes the second surface of the semiconductor substrate.

3. The microelectronic assembly of claim 2, wherein the inductor comprises at least one coil wrapped around an inductor center point on the semiconductor substrate and the first and second trenches are formed around the inductor center point, the first trench being between the inductor center point and the second trench and the first and second trenches have a substantially circular shape and the cavity has an annular ring shape.

4. The microelectronic assembly of claim 3, further comprising a plurality of support walls interconnecting the first and second etch stop walls.

5. The microelectronic assembly of claim 4, further comprising an annular support member extending from an inner surface of the cavity, the annular support member comprising the etch stop material.

6. The microelectronic assembly of claim 5, further comprising a metal layer formed on the first surface of the semiconductor substrate over the sealing layer.

7. The microelectronic assembly of claim 6, wherein the etch stop layer comprises an oxide material.

8. The microelectronic assembly of claim 7, wherein the inductor comprises at least one metal line formed over the second surface of the semiconductor substrate.

9. The microelectronic assembly of claim 7, wherein the semiconductor substrate comprises silicon.

11. The microelectronic assembly of claim 7, wherein at least a portion of the inductor is positioned over the cavity.

12. The microelectronic assembly of claim 8, wherein the inductor comprises a coil wrapped around an inductor center point on the semiconductor substrate.

13. The microelectronic assembly of claim 9, wherein the first and second lateral etch stop walls are formed around the inductor center point.

10. A microelectronic assembly, comprising:

a semiconductor substrate having first and second opposing sides;

first and second lateral etch stop walls within the semiconductor substrate;

an inductor on the first surface of the semiconductor substrate;

a cavity within the semiconductor substrate between the first and second lateral etch stop walls;

an etch hole formed though the second surface of the semiconductor substrate to the cavity; and

a sealing layer formed over the etch hole to seal the cavity.

14. The microelectronic assembly of claim 10, wherein the first lateral etch stop wall is positioned between the inductor center point and the second lateral etch stop wall and both the first and second lateral etch stop walls are centered on the inductor center point.

15. A microelectronic assembly, comprising:

a semiconductor substrate having first and second opposing surfaces and first and second trenches on the first surface of a semiconductor substrate, the semiconductor substrate comprising a semiconductor material;

an etch stop layer formed over the first surface of the semiconductor substrate, the etch stop layer filling the first and second trenches;

an inductor on the first surface of the semiconductor substrate;

an etch hole through the second surface of the semiconductor substrate to expose the semiconductor material between the first and second trenches;

a cavity within the semiconductor substrate between the first and second trenches and adjacent to the etch hole; and

a sealing layer formed over the second surface of the semiconductor substrate to seal the cavity.

16. The microelectronic assembly of claim 15, wherein the first surface of the semiconductor substrate is an upper surface and the second surface of the semiconductor substrate is a lower surface.

17. The microelectronic assembly of claim 16, wherein the first and second trenches are formed around a trench center point with the first trench being positioned between the trench center point and the second trench.

18. The microelectronic assembly of claim 17, wherein the inductor comprises a coil wrapped around the trench center point and at least a portion of the coil is positioned over the cavity.

19. The microelectronic assembly of claim 18, wherein the first and second trenches have a substantially circular shape and the cavity has an annular ring shape.

20. The microelectronic assembly of claim 19, further comprising a metal layer formed on the lower surface of the semiconductor substrate over the sealing layer.