Semiconductor device and method for manufacturing the same

• US 20080290490A1
• Filed: 02/12/2008
• Published: 11/27/2008
• Est. Priority Date: 02/22/2007
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Sugiura, Kazuhiko, Fujii, Tetsuo
• Granted Patent: US 7,859,091 B2
• Time in Patent Office: Days
• US Class Current: 257/684
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes: a first substrate made of semiconductor and having first regions, which are insulated from each other and disposed in the first substrate; and a second substrate having electric conductivity and having second regions and insulation trenches. Each insulation trench penetrates the second substrate so that the second regions are insulated from each other. The first substrate provides a base substrate, and the second substrate provides a cap substrate. The second substrate is bonded to the first substrate so that a sealed space is provided between a predetermined surface region of the first substrate and the second substrate. The second regions include an extraction conductive region, which is coupled with a corresponding first region.

Claims

1. A semiconductor device comprising:

a first substrate made of semiconductor and having a plurality of first regions, wherein the first regions are insulated from each other and disposed in a surface portion of the first substrate, and wherein each first region is a semiconductor region; and

a second substrate having electric conductivity and having a plurality of second regions and a plurality of insulation trenches, wherein each insulation trench penetrates the second substrate so that the second regions are insulated from each other, and wherein each second region is a conductive region, wherein

the first substrate provides a base substrate, and the second substrate provides a cap substrate,

the second substrate is bonded to the first substrate so that a sealed space is provided between a predetermined surface region of the first substrate and the second substrate, and

the second regions include an extraction conductive region, which is coupled with a corresponding first region.

2. The semiconductor device according to claim 1, wherein

the second substrate further includes a concavity, which faces the predetermined surface region of the first substrate, and

the second substrate is bonded to the first substrate at a periphery of the concavity.

3. The semiconductor device according to claim 2, wherein

the second substrate further includes an insulation film, which is disposed on a predetermined position of the concavity.

4. The semiconductor device according to claim 1, wherein

the first substrate further includes a conductive convexity, which is disposed on one of the first regions of the first substrate, and

the second substrate is bonded to the conductive convexity of the first substrate.

5. The semiconductor device according to claim 4, wherein

the conductive convexity is made of single crystal silicon, poly-crystal silicon or metal.

6. The semiconductor device according to claim 1, wherein

the second substrate further includes a conductive convexity on one of the second regions,

the conductive convexity faces a corresponding first region of the first substrate, and

the conductive convexity of the second substrate is bonded to the first substrate.

7. The semiconductor device according to claim 6, wherein

the conductive convexity provides a first wiring pattern, which is electrically coupled with the one of the second regions through an insulation film.

8. The semiconductor device according to claim 7, wherein

the second substrate is one of a plurality of second substrates,

each second substrate further includes a second wiring pattern, which is disposed on a side opposite to the first wiring pattern, and

the plurality of second substrates is stacked on the first substrate.

9. The semiconductor device according to claim 1, wherein

the first substrate is made of single crystal silicon.

10. The semiconductor device according to claim 1, wherein

the first substrate is made of a SOI substrate having a SOI layer, an embedded oxide film and a silicon substrate, which are stacked in this order,

the first regions are disposed in the SOI layer, and

the first regions are insulated from each other with a separation trench, which reaches to the embedded oxide film.

11. The semiconductor device according to claim 10 further comprising:

a physical quantity sensor having a movable electrode and a fixed electrode for detecting a physical quantity applied to the sensor, wherein

one of the plurality of first regions provides a movable semiconductor region, and another one of the plurality of first regions provides a fixed semiconductor region,

the movable semiconductor region has the movable electrode,

the embedded oxide film under the movable electrode is removed by a sacrifice etching method so that the movable electrode is displaceable and separated from the silicon substrate,

the fixed semiconductor region has the fixed electrode, which faces the movable electrode,

the movable electrode and the fixed electrode provide a capacitance therebetween in such a manner that a space between the movable electrode and the fixed electrode provides a dielectric layer,

the second regions further include a first extraction conductive region and a second extraction conductive region,

the first extraction conductive region is coupled with the movable semiconductor region, and the second extraction conductive region is coupled with the fixed semiconductor region,

the movable electrode is displaceable in accordance with the applied physical quantity along with a direction perpendicular to the first substrate, and

the sensor detects the physical quantity by measuring capacitance change according to displacement of the movable electrode.

12. The semiconductor device according to claim 11, wherein

the physical quantity is acceleration or angular speed.

13. The semiconductor device according to claim 10 further comprising:

a MEMS resonant device having a resonant element, wherein

one of the plurality of first regions provides a resonant semiconductor region,

the resonant semiconductor region has the resonant element,

the embedded oxide film under the resonant element is removed by a sacrifice etching method so that the resonant element is displaceable and separated from the silicon substrate,

the resonant element is disposed in the sealed space, and

the resonant element is energized from the extraction conductive region so that the resonant element resonates and generates a voltage having a predetermined frequency.

14. The semiconductor device according to claim 1 further comprising:

an infrared sensor for detecting an infrared light, wherein

the infrared sensor is disposed on the predetermined surface region of the first substrate,

the infrared sensor outputs an output voltage corresponding to the infrared light, and

the output voltage is output through the extraction conductive region.

15. The semiconductor device according to claim 1 further comprising:

a magnetic sensor for detecting a magnetic field, wherein

the magnetic sensor is disposed on the predetermined surface region of the first substrate,

the magnetic sensor is disposed in the sealed space,

the magnetic sensor outputs an output voltage corresponding to the magnetic field, and

the output voltage is output through the extraction conductive region.

16. The semiconductor device according to claim 1 further comprising:

an IC circuit disposed on the predetermined surface region of the first substrate, wherein

the IC circuit is electrically coupled with an external circuit through the extraction conductive region.

17. The semiconductor device according to claim 1, wherein

the second substrate is made of single silicon.

18. The semiconductor device according to claim 17, wherein

the plurality of first regions includes a single crystal conductive region and a poly-crystal conductive region,

the single crystal conductive region is made of single crystal silicon, and the poly-crystal conductive region is made of poly crystal silicon, and

the extraction conductive region is made of poly crystal silicon.

19. The semiconductor device according to claim 1, wherein

the second substrate is made of a SOI substrate having a SOI layer, an embedded oxide film and a silicon substrate, which are stacked in this order, and

the second regions are insulated from each other with a separation trench, which reaches to the embedded oxide film.

20. The semiconductor device according to claim 19, wherein

the plurality of second regions includes a single crystal conductive region and a poly crystal conductive region,

the single crystal conductive region is disposed in the SOI layer, and made of single crystal silicon, and

the poly-crystal conductive region is made of poly-crystal silicon, and the extraction conductive region is made of poly-crystal silicon.

21. The semiconductor device according to claim 17 further comprising:

an IC circuit disposed on one of the plurality of second regions, wherein

the IC circuit is disposed opposite to the first substrate.

22. The semiconductor device according to claim 1, wherein

the extraction conductive region is surrounded with at least one of the plurality of second regions, and

the one of the plurality of second regions has an electric potential, which is fixed to a predetermined potential.

23. The semiconductor device according to claim 22, wherein

the predetermined potential is a ground potential.

24. The semiconductor device according to claim 1, wherein

the first substrate and the second substrate are made of silicon, and

the first substrate and the second substrate are bonded to each other with a silicon direct bonding structure.

25. The semiconductor device according to claim 1, wherein

the first substrate and the second substrate are made of silicon, and

the first substrate and the second substrate are bonded to each other with a silicon-gold eutectic bonding structure.

26. The semiconductor device according to claim 1, wherein

the first substrate and the second substrate are bonded to each other with a conductive adhesive.

27. A method for manufacturing a semiconductor device comprising:

preparing a first substrate made of semiconductor, wherein the first substrate includes a plurality of first regions, which are insulated from each other and disposed in a surface portion of the first substrate, and wherein each first region is a semiconductor region;

preparing a second substrate having electric conductivity and including a plurality of second regions and a plurality of insulation trenches, wherein each insulation trench penetrates the second substrate so that the second regions are insulated from each other, and wherein each second region is a conductive region;

bonding the second substrate to the first substrate so that a sealed space is formed between a predetermined surface region of the first substrate and the second substrate; and

electrically coupling one of the second regions and a corresponding one of the first regions so that the one of the second regions provides an extraction conductive region, wherein

the first substrate provides a base substrate, and the second substrate provides a cap substrate.

28. The method according to claim 27, wherein

the preparing the second substrate includes:

forming a concavity on a first side of the second substrate so as to face the predetermined surface region of the first substrate;

forming a plurality of primary trenches on the first side of the second substrate, wherein each primary trench has a predetermined depth; and

grinding a second side of the second substrate until a bottom of the primary trench is exposed from the second side of the second substrate, wherein the exposed primary trench provides the insulation trench,

the bonding the second substrate to the first substrate includes;

arranging the concavity of the second substrate to face the predetermined surface region of the first substrate; and

bonding the second substrate to the first substrate at a periphery of the concavity.

29. The method according to claim 27, wherein

the preparing the second substrate includes:

forming a plurality of primary trenches on a first side of the second substrate, wherein each primary trench has a predetermined depth;

grinding a second side of the second substrate until a bottom of the primary trench is exposed from the second side of the second substrate, wherein the exposed primary trench provides the insulation trench; and

forming a concavity on the second side of the second substrate so as to face the predetermined surface region of the first substrate after the grinding the second side of the second substrate, and

the bonding the second substrate to the first substrate includes;

arranging the concavity of the second substrate to face the predetermined surface region of the first substrate; and

bonding the second substrate to the first substrate at a periphery of the concavity.

30. The method according to claim 27, wherein

the second substrate is made of single crystal silicon,

the preparing the second substrate includes:

forming a plurality of primary trenches on a first side of the second substrate, wherein each primary trench has a predetermined depth;

forming a sidewall oxide film on a sidewall of each primary trench;

forming a poly crystal silicon film on the sidewall oxide film in each primary trench so as to fill the primary trench with the poly crystal silicon film;

grinding a second side of the second substrate until a bottom of the poly crystal silicon film in each primary trench is exposed from the second side of the second substrate, wherein the exposed primary trench with the sidewall oxide film provides the insulation trench; and

forming a concavity on the second side of the second substrate so as to face the predetermined surface region of the first substrate after the grinding the second side of the second substrate, and

the bonding the second substrate to the first substrate includes;

arranging the concavity of the second substrate to face the predetermined surface region of the first substrate; and

bonding the second substrate to the first substrate at a periphery of the concavity.

31. The method according to claim 27, wherein

the second substrate is made of a SOI substrate having a SOI layer, an embedded oxide film and a silicon substrate, which are stacked in this order,

the preparing the second substrate includes:

forming a plurality of primary trenches in the SOI layer on a first side of the second substrate, wherein each primary trench penetrates the SOI layer and the embedded oxide film;

forming a sidewall oxide film on a sidewall of each primary trench;

forming a poly crystal silicon film on the sidewall oxide film in each primary trench so as to fill the primary trench with the poly crystal silicon film;

etching a second side of the second substrate until the embedded oxide film and the sidewall oxide film in each primary trench is exposed from the second side of the second substrate, wherein the etching the second side of the second substrate provides to form a concavity on the second side of the second substrate so as to face the predetermined surface region of the first substrate; and

grinding the second side of the second substrate until a bottom of the poly crystal silicon film in each primary trench is exposed from the second side of the second substrate, wherein the exposed primary trench with the oxide film provides the insulation trench, and, the bonding the second substrate to the first substrate includes;

arranging the concavity of the second substrate to face the predetermined surface region of the first substrate; and

bonding the second substrate to the first substrate at a periphery of the concavity.

32. The method according to claim 27, wherein

the preparing the first substrate includes:

forming the plurality of first regions in the surface portion of the first substrate; and

forming a conductive convexity on one of the first regions, and

in the bonding the second substrate to the first substrate, the second substrate is bonded to the conductive convexity of the first substrate.

33. The method according to claim 27, wherein

the preparing the second substrate includes:

forming a plurality of primary trenches on a first side of the second substrate, wherein each primary trench has a predetermined depth;

grinding a second side of the second substrate until a bottom of the primary trench is exposed from the second side of the second substrate, wherein the exposed primary trench provides the insulation trench; and

forming a convexity on one of the second regions so as to face a corresponding first region of the first substrate, and

in the bonding the second substrate to the first substrate, the conductive convexity of the second substrate is bonded to the first substrate.

34. The method according to claim 33, wherein

the forming the convexity provides to form a wiring pattern, which is electrically coupled with the one of the second regions through an insulation film.

35. The method according to claim 27, wherein

the first substrate and the second substrate are made of silicon, and

in the bonding the second substrate to the first substrate, the first substrate and the second substrate are bonded to each other with a silicon direct bonding structure.