Charging Circuit for Bootstrap Capacitor and Integrated Driver Circuit Using Same

• US 20080290841A1
• Filed: 05/23/2007
• Published: 11/27/2008
• Est. Priority Date: 05/23/2007
• Status: Abandoned Application

• Current Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Original Assignee: Richtek Technology Corporation (MediaTek, Inc.)
• Inventors: Cheng, Chien-Hsing, Chang, Kuang-Ming
• Application Number:
  US11/752,441
• Publication Number:
  US 20080290841A1
• Time in Patent Office: Days
• US Class Current: 320/166
• CPC Class Codes: H02J 7/0068 Battery or charger load switching, e.g. concurrent charging and load supply H02J7/0013 takes precedence
• CPC Class Codes: H02J 7/345 using capacitors as storage or buffering devices

Abstract

The present invention discloses a charging circuit for charging a bootstrap capacitor from a supply voltage, the charging circuit comprising: a depletion mode transistor, having a first end of its source/drain electrically connected with the supply voltage, a gate electrically connected to the supply voltage, and a second end of its source/drain electrically connected with the bootstrap capacitor. Preferably, a diode is provided between the supply voltage and the depletion mode transistor.

Claims

1. A charging circuit for charging a bootstrap capacitor from a supply voltage, the charging circuit comprising:

a depletion mode transistor, having a first end of its source/drain electrically connected with the supply voltage, a gate electrically connected to the supply voltage, and a second end of its source/drain electrically connected with the bootstrap capacitor.

2. The charging circuit of claim 1, further comprising a diode having an anode electrically connected with the supply voltage and a cathode electrically connected with the first end of the depletion mode transistor.

3. The charging circuit of claim 1, wherein the depletion mode transistor is a lateral diffused metal-oxide-silicon (LDMOS) device.

4. An integrated driver circuit for controlling at least a power transistor, the integrated driver circuit comprising:

an up-gate driver circuit for controlling a first power transistor, the up-gate driver circuit having a first voltage terminal electrically connected with a first voltage node, and a second voltage terminal electrically connected with a second voltage node; and

a depletion mode transistor, having a first end of its source/drain electrically connected with a supply voltage, a gate electrically connected to the supply voltage, and a second end of its source/drain electrically connected with the first voltage node.

5. The integrated driver circuit of claim 4, wherein the first voltage node and the second voltage node are respectively electrically connected with two ends of a bootstrap capacitor.

6. The integrated driver circuit of claim 5, wherein the bootstrap capacitor is located external to the integrated driver circuit.

7. The integrated driver circuit of claim 4, further comprising a diode having an anode electrically connected with the supply voltage and a cathode electrically connected with the first end of the depletion mode transistor.

8. The integrated driver circuit of claim 4, further comprising a low-gate driver circuit for controlling a second power transistor.

9. The integrated driver circuit of claim 4, wherein the depletion mode transistor is a lateral diffused metal-oxide-silicon (LDMOS) device.

10. A half-bridge power supplier circuit for supplying a voltage to a load, the half-bridge power supplier circuit comprising:

a first and a second power transistors electrically connected with each other;

an up-gate driver circuit for controlling the first power transistor, the up-gate driver circuit having a first voltage terminal electrically connected with a first voltage node, and a second voltage terminal electrically connected with a second voltage node;

a low-gate driver circuit for controlling the second power transistor;

a bootstrap capacitor electrically connected between the first voltage node and the second voltage node; and

a depletion mode transistor, having a first end of its source/drain electrically connected with a first supply voltage, a gate electrically connected to the first supply voltage, and a second end of its source/drain electrically connected with the first voltage node.

11. The half-bridge power supplier circuit of claim 10, further comprising a diode having an anode electrically connected with the first supply voltage and a cathode electrically connected with the first end of the depletion mode transistor.

12. The half-bridge power supplier circuit of claim 10, wherein the first power transistor having one end electrically connected with a second supply voltage, the second supply voltage being higher than the first supply voltage.

13. The half-bridge power supplier circuit of claim 10, wherein the depletion mode transistor is a lateral diffused metal-oxide-silicon (LDMOS) device.