PROBE NEEDLE PROTECTION METHOD FOR HIGH CURRENT PROBE TESTING OF POWER DEVICES

• US 20080290882A1
• Filed: 05/23/2007
• Published: 11/27/2008
• Est. Priority Date: 05/23/2006
• Status: Active Grant

• Current Assignee: Integrated Technology Corporation
• Original Assignee: Integrated Technology Corporation
• Inventors: Rogers, Gary, Lohr, Dave, Clauter, Steve, Schwartz, Rodney, Ukai, Taichi, Lambright, Joe
• Granted Patent: US 7,521,947 B2
• Time in Patent Office: Days
• US Class Current: 324/755.11
• CPC Class Codes: G01R 1/06766 Input circuits therefor
• CPC Class Codes: G01R 1/36 Overload-protection arrangements or circuits for electric measuring instruments
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A test system, apparatus and method for applying high current test stimuli to a semiconductor device in wafer or chip form includes a plurality of probes for electrically coupling to respective contact points on the semiconductor device, a plurality of current limiters electrically coupled to respective ones of the plurality of probes, and a current sensor electrically coupled to the plurality of probes. The current limiters are operative to limit current flow passing through a respective probe, and the current sensor is operative to provide a signal when detected current in any contact of the plurality of probes exceeds a threshold level.

Claims

1. A test apparatus for applying high current test stimuli to a semiconductor device in wafer or chip form, said semiconductor device including a plurality of contact points, comprising:

a plurality of probes for electrically coupling to respective ones of the plurality of contact points on the semiconductor device

a plurality of current limiters electrically coupled to respective ones of the plurality of probes, said current limiters operative to limit current flow in a corresponding probe; and

a current sensor electrically coupled to each of the plurality of probes, said current sensor operative to provide a signal when detected current in any probe exceeds a predetermined level.

2. The test apparatus of claim 1, further comprising an inhibit circuit operatively coupled to said current sensor, wherein when the current sensor generates the signal, the inhibit circuit prevents current flow through each of the probes.

3. The test apparatus of claim 1, wherein the semiconductor device is at least one of an integrated circuit or a power semiconductor.

4. The test apparatus of claim 1, wherein said current limiters comprise a power transistor in combination with control circuitry, said control circuitry operative to limit the current flow through the power transistor.

5. The test apparatus of claim 4, wherein said power transistor is a power metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bi-polar transistor (IGBT).

6. The test apparatus of claim 1, wherein said current sensor comprises a current limit sensing circuit operative to detect when any one of the current limiters transition into a constant current mode.

7. The test apparatus of claim 1, further comprising a silicon controlled rectifier (SCR) device coupled between an emitter/drain terminal and a collector/source terminal of the semiconductor device, wherein said current sensor comprises a current limit sensing circuit that drives the SCR device so as to shunt current away from the emitter/drain and collector/source of the semiconductor device.

8. The test apparatus of claim 1, further comprising a verification device operative to determine if a resistance between a probe/contact interface defined between a probe and a corresponding contact point is within predetermined limits.

9. The test apparatus of claim 8, wherein said verification device comprises measurement circuitry to sense a voltage drop across each individual probe/contact interface.

10. The test apparatus of claim 9, wherein said measurement circuitry is operative to inject a measurement current through each probe and to sense a resulting voltage drop across the probe/contact interface.

11. The test apparatus of claim 1, wherein each of the plurality of current limiters is operative to be enabled or disabled independent of other ones of the plurality of current limiters.

12. The test apparatus of claim 1, wherein the current limiters are configured as open loop controllers.

22. The test apparatus according to claim 1, wherein the current limiters limit the current flow in each respective probe to a predetermined level.

13. A method for applying high current test stimuli to a semiconductor device in wafer or chip form, said semiconductor device including a plurality of contact points, comprising:

coupling a plurality of probes to at least one of the plurality of contact points on the semiconductor device;

independently limiting current flow through each probe of the plurality of probes to a predetermined level; and

providing a signal when detected current in any probe exceeds a predetermined level.

14. The method of claim 13, further comprising inhibiting current flow through the probes upon detection of a fault condition.

15. The method of claim 13, further comprising determining if a resistance between a contact interface defined between a probe and a corresponding contact point is within predetermined limits.

16. The method of claim 15, wherein determining the resistance includes measuring a voltage drop across each individual contact interface.

17. The method of claim 16, wherein measuring a voltage drop includes injecting a measurement current through each probe and measuring the resulting voltage drop across the contact interface.

18. The method of claim 13, wherein independently limiting current includes using an open loop controller to limit the current.

19. The method of claim 13, further comprising generating a signal when the current flow in any probe of the plurality of probes exceeds the predetermined level.

20. The method of claim 19, further comprising inhibiting current flow through the plurality of probes upon generation of the signal.

23. The method according to claim 13, further comprising protecting the probes from an over-voltage condition based on a voltage drop across the current limiters.

21. (canceled)

24. A test apparatus for applying high current test stimuli to a semiconductor device in wafer or chip form, said semiconductor device including a plurality of contact points, comprising:

a plurality of probes for electrically coupling to at least one of the plurality of contact points on the semiconductor device

a plurality of current limiters electrically coupled to respective ones of the plurality of probes, said current limiters operative to limit current flow in a corresponding probe;

a voltage protection circuit electrically coupled to said plurality of current limiters, said voltage protection circuit operative to protect the plurality of probes from an over-voltage condition; and

a trigger circuit electrically coupled to each of the plurality of current limiters and to the protection circuit, said trigger circuit operative to detect a voltage drop across the current limiters, and when the voltage drop across any current limiter exceeds a predetermined level, the trigger circuit is operative to command the voltage protection circuit to enter a protection mode.

25. The test apparatus according to claim 24, wherein said protection circuit comprises a silicon controlled rectifier (SCR) device coupled between an emitter/drain terminal and a collector/source terminal of the test apparatus, wherein said trigger circuit comprises a voltage sensing circuit that fires the SCR device so as to shunt current away from the emitter/drain and collector/source of the test apparatus.