MOSFET gate drive with reduced power loss

• US 20080290911A1
• Filed: 08/08/2007
• Published: 11/27/2008
• Est. Priority Date: 05/21/2007
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K.
• Granted Patent: US 7,812,647 B2
• Time in Patent Office: Days
• US Class Current: 327/109
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/18 Modifications for indicating state of switch
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 2217/94031 Calibration involving digital processing

Abstract

A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A feedback circuit may be used to assure that the magnitude of current in the power MOSFET in its low-current condition is correct. Alternatively, a trimming process may be used to correct the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition.

Claims

1. A combination comprising a gate driver and a power MOSFET, an output terminal of the gate driver being connected to a gate terminal of the power MOSFET, the gate driver further comprising:

a first input terminal and a second input terminal, the first input terminal being connected to a first voltage source, the second input terminal being connected to a second voltage source;

a switching element for switching the output terminal between the first input terminal and second input terminal;

wherein a first voltage provided by the first voltage source causes the power MOSFET to be in a fully on condition when delivered to the gate terminal and a second voltage provided by the second voltage source causes the power MOSFET to be in a low-current condition when delivered to the gate terminal.

2. The combination of claim 1 further comprising a buffer connected to the gate driver for switching the output terminal repeatedly between the first and second input terminals.

3. The combination of claim 1 wherein the switching element comprises a CMOS pair, a first MOSFET of the CMOS pair being connected between the first input terminal and the output terminal, a second MOSFET of the CMOS pair being connected between the second input terminal and the output terminal.

4. The combination of claim 1 wherein the gate driver comprises a third input terminal, the third input terminal being connected to a source terminal of the power MOSFET, the switching element being capable of switching the output terminal between the first, second and third input terminals.

5. The combination of claim 4 wherein the gate driver comprises a CMOS pair and a third MOSFET, a first MOSFET of the CMOS pair being connected between the first input terminal and the output terminal, a second MOSFET of the CMOS pair being connected between the third input terminal and the output terminal, the third MOSFET being connected between the second input terminal and the output terminal.

6. The combination of claim 1 wherein the power MOSFET is connected with a load in a power circuit, the combination further comprising a feedback circuit connected between the power circuit and the second terminal of the gate driver, the feedback circuit being for generating an error signal which maintains the current in the low-current condition of the power MOSFET at a target value.

7. The combination of claim 6 wherein the feedback circuit comprises a current sensor connected in the power circuit and an amplifier and wherein the second voltage source comprises a variable voltage source, the current sensor being connected to a first input terminal of the amplifier, a second input terminal of the amplifier being connected to a reference current source, an output of the amplifier being connected to the variable voltage source.

8. The combination of claim 6 wherein the power circuit includes a sense resistor and the feedback circuit comprises an amplifier and a reference voltage source, a first input terminal of the amplifier being connected to the sense resistor, a second input terminal of the amplifier being connected to the reference voltage source, and an output terminal of the amplifier being connected to the second terminal of the gate driver.

9. The combination of claim 6 wherein the feedback circuit comprises:

a current mirror arrangement for generating a mirror current, the size of the mirror current being proportional to the size of the current in the power circuit;

a sense resistor connected to the current mirror arrangement such that the mirror current flows through the sense resistor; and

an amplifier, a first input terminal of the amplifier being connected to a reference voltage source, a second input terminal of the amplifier being connected to the sense resistor, and an output terminal of the amplifier being connected to the second input terminal of the gate driver.

10. The combination of claim 9 wherein the feedback circuit comprises. a second MOSFET connected in series with the power MOSFET.

11. The combination of claim 1 wherein the power MOSFET is connected with a load in a power circuit and the second voltage source comprises a variable voltage source, the combination further comprising a current sensor connected in the power circuit and a trim circuit connected to the current source and the variable voltage source, the trim circuit adapted to adjust the magnitude of the second voltage in response to an output signal from the current sensor.

12. The combination of claim 11 wherein the trim circuit comprises a plurality of resistors and a plurality of one-time-programmable MOSFETs, each of the resistors being connected in parallel with a corresponding one of the one-time-programmable MOSFETs.

13. The combination of claim 1 wherein the power MOSFET is connected with a load in a power circuit, the combination further comprising:

a current mirror MOSFET, the gate and drain terminals of the current mirror MOSFET being shorted together and connected to the second terminal of the gate driver;

a current sensor connected in the power circuit;

a variable current source connected to the current mirror MOSFET; and

a trim circuit connected to the current source and the variable current source, the trim circuit being adapted to adjust the magnitude of a current supplied by the variable current source in response to an output signal from the current sensor.

14. The combination of claim 1 wherein the power MOSFET is connected with a load in a power circuit, the combination further comprising:

a current mirror MOSFET, the gate and drain terminals of the current mirror MOSFET being shorted together and connected to the second terminal of the gate driver; and

a current source connected to the current mirror MOSFET, the current source adapted to supply a current having a magnitude equal to a specified proportion of a desired magnitude of a current in the power MOSFET in the low-current condition.

15. The combination of claim 14 wherein the current source comprises a variable current source, the combination further comprising a digital-to-analog converter connected to an input terminal of the variable current source and a digital device connected to an input terminal of the digital-to-analog converter.

16. The combination of claim 1 wherein the power MOSFET is a component of a boost converter, the power MOSFET being connected in series with an inductor, a synchronous rectifier MOSFET being connected between an output terminal of the boost converter and a common node between the power MOSFET and the inductor.

17. The combination of claim 1 wherein the power MOSFET is a component of a Buck converter, the power MOSFET being connected in series with a synchronous rectifier MOSFET, an inductor being connected between an output terminal of the Buck converter and a common node between the power MOSFET and the synchronous rectifier MOSFET.